From edfba7e707a4f2f2e800843a7ef980c27d7f4eff Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Fri, 11 Jul 2008 16:54:57 +0000 Subject: Port a shift-by-1 optimization from LegalizeDAG: it was presumably added after the rest of the code was copied to LegalizeTypes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53459 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib/CodeGen') diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index a1840f130f..4e3e21732b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1556,6 +1556,13 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, } else if (Amt == NVTBits) { Lo = DAG.getConstant(0, NVT); Hi = InL; + } else if (Amt == 1) { + // Emit this X << 1 as X+X. + SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); + SDOperand LoOps[2] = { InL, InL }; + Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) }; + Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); } else { Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); Hi = DAG.getNode(ISD::OR, NVT, -- cgit v1.2.3-70-g09d2