From cfb22d3c14b53bc73ec90f7d471c2d2d2453cf03 Mon Sep 17 00:00:00 2001 From: Anand Shukla Date: Tue, 25 Jun 2002 20:55:50 +0000 Subject: changes to make it compatible with 64bit gcc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2791 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/InstrSelection/InstrSelection.cpp | 5 +++-- lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'lib/CodeGen') diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp index b27f9022bb..c43f8ddf84 100644 --- a/lib/CodeGen/InstrSelection/InstrSelection.cpp +++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp @@ -27,6 +27,7 @@ #include "Support/CommandLine.h" #include using std::cerr; +using std::vector; //******************** Internal Data Declarations ************************/ @@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target) //------------------------------------------------------------------------- void -InsertPhiElimInstructions(BasicBlock *BB, const vector& CpVec) +InsertPhiElimInstructions(BasicBlock *BB, const std::vector& CpVec) { Instruction *TermInst = (Instruction*)BB->getTerminator(); MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst); @@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt, // if (treeRoot->opLabel != VRegListOp) { - vector minstrVec; + std::vector minstrVec; InstructionNode* instrNode = (InstructionNode*)treeRoot; assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode); diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index c7c9756ce7..e884463ae2 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -28,6 +28,7 @@ #include #include using std::cerr; +using std::vector; RegAllocDebugLevel_t DEBUG_RA; static cl::Enum DEBUG_RA_c(DEBUG_RA, "dregalloc", -- cgit v1.2.3-70-g09d2