From 79a796c2b17c7ebd4dd489b5de1078fc2148adba Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 12 Jul 2008 01:56:02 +0000 Subject: Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g. 8 %reg1024 = IMPLICIT_DEF 12 %reg1024 = INSERT_SUBREG %reg1024, %reg1025, 2 The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53503 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LiveIntervalAnalysis.cpp | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'lib/CodeGen') diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 974571944a..85c837ae0b 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -1047,6 +1047,18 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, } } + if (HasUse && !li.liveAt(getUseIndex(index))) + // Must be defined by an implicit def. It should not be spilled. Note, + // this is for correctness reason. e.g. + // 8 %reg1024 = IMPLICIT_DEF + // 12 %reg1024 = INSERT_SUBREG %reg1024, %reg1025, 2 + // The live range [12, 14) are not part of the r1024 live interval since + // it's defined by an implicit def. It will not conflicts with live + // interval of r1025. Now suppose both registers are spilled, you can + // easier see a situation where both registers are reloaded before + // the INSERT_SUBREG and both target registers that would overlap. + HasUse = false; + // Update stack slot spill weight if we are splitting. float Weight = getSpillWeight(HasDef, HasUse, loopDepth); if (!TrySplit) @@ -1228,6 +1240,17 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, unsigned index = getInstructionIndex(MI); if (index < start || index >= end) continue; + if (O.isUse() && !li.liveAt(getUseIndex(index))) + // Must be defined by an implicit def. It should not be spilled. Note, + // this is for correctness reason. e.g. + // 8 %reg1024 = IMPLICIT_DEF + // 12 %reg1024 = INSERT_SUBREG %reg1024, %reg1025, 2 + // The live range [12, 14) are not part of the r1024 live interval since + // it's defined by an implicit def. It will not conflicts with live + // interval of r1025. Now suppose both registers are spilled, you can + // easier see a situation where both registers are reloaded before + // the INSERT_SUBREG and both target registers that would overlap. + continue; RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef())); } std::sort(RewriteMIs.begin(), RewriteMIs.end(), RewriteInfoCompare()); -- cgit v1.2.3-70-g09d2