From 0ca67332fa4eaed35e8e85b2c935500798ea6c2a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 12 Dec 2006 21:21:32 +0000 Subject: Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32493 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/CodeGen') diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index c6ca13e2a3..c112b873b7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3942,6 +3942,9 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, else Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); return DAG.getCopyToReg(getRoot(), Reg, Op); + } else if (SrcVT == MVT::f32 || SrcVT == MVT::f64) { + return DAG.getCopyToReg(getRoot(), Reg, + DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); } else { // The src value is expanded into multiple registers. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, -- cgit v1.2.3-70-g09d2