From f07fc974d330fa355ba60f23828657f54f97e5aa Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 29 Apr 2010 23:47:46 +0000 Subject: Reject really weird coalescer case when trying to merge identical subregisters of different register classes. e.g. %reg1048:3 = EXTRACT_SUBREG %RAX, 3 Where %reg1048 is a GR32 register. This is not impossible to handle, but it is pretty hard and very rare. This should unbreak the dragonegg builder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102672 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SimpleRegisterCoalescing.cpp | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp') diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index e7c758db09..da96f232b8 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -1394,6 +1394,13 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { return false; // Not coalescable. } + // We cannot handle dual subreg indices and mismatched classes at the same + // time. + if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) { + DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n"); + return false; + } + // Check that a physical source register is compatible with dst regclass if (SrcIsPhys) { unsigned SrcSubReg = SrcSubIdx ? -- cgit v1.2.3-70-g09d2