From 92efda7e9183ae16bde7a3ad96b682e779d89cf3 Mon Sep 17 00:00:00 2001 From: Cameron Zwarich Date: Tue, 22 Feb 2011 00:46:27 +0000 Subject: Merge information about the number of zero, one, and sign bits of live-out registers at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp') diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 452f5614b7..c1be3e95fc 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -644,7 +644,10 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, !RegisterVT.isInteger() || RegisterVT.isVector() || !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i])) continue; - + + if (FuncInfo.PHIDestRegs.count(Regs[Part+i]) && !FuncInfo.AllPredsVisited) + continue; + const FunctionLoweringInfo::LiveOutInfo &LOI = FuncInfo.LiveOutRegInfo[Regs[Part+i]]; @@ -6466,6 +6469,9 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { } } + if (!EnableFastISel) + FuncInfo.PHISrcToDestMap[Reg] = FuncInfo.ValueMap[PN]; + // Remember that this register needs to added to the machine PHI node as // the input for this MBB. SmallVector ValueVTs; -- cgit v1.2.3-18-g5258