From 13ec702c430b91ee49b9e6d9581cd95412f216c8 Mon Sep 17 00:00:00 2001 From: Jim Laskey Date: Tue, 1 Aug 2006 14:21:23 +0000 Subject: Introducing plugable register allocators and instruction schedulers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29434 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocSimple.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib/CodeGen/RegAllocSimple.cpp') diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index c6faead658..bd20cd04c5 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachinePassRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" @@ -33,6 +34,10 @@ namespace { static Statistic<> NumStores("ra-simple", "Number of stores added"); static Statistic<> NumLoads ("ra-simple", "Number of loads added"); + static RegisterRegAlloc + simpleRegAlloc("simple", " simple register allocator", + createSimpleRegisterAllocator); + class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass { MachineFunction *MF; const TargetMachine *TM; -- cgit v1.2.3-70-g09d2