From 418da55c89c9ba355b51dceecb16f4388ef35119 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 21 Jun 2004 13:10:56 +0000 Subject: Rename Interval class to LiveInterval to avoid conflicting with the already existing llvm::Interval class. Patch contributed by Vladimir Prus! http://mail.cs.uiuc.edu/pipermail/llvmbugs/2004-June/000710.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14281 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocLinearScan.cpp | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'lib/CodeGen/RegAllocLinearScan.cpp') diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index bab8717180..285f493fff 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -39,7 +39,7 @@ namespace { const TargetMachine* tm_; const MRegisterInfo* mri_; LiveIntervals* li_; - typedef std::list IntervalPtrs; + typedef std::list IntervalPtrs; IntervalPtrs unhandled_, fixed_, active_, inactive_, handled_; std::auto_ptr prt_; @@ -374,12 +374,12 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur) if (cur->weight <= minWeight) { DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';); int slot = vrm_->assignVirt2StackSlot(cur->reg); - std::vector added = + std::vector added = li_->addIntervalsForSpills(*cur, *vrm_, slot); // merge added with unhandled - std::vector::iterator addedIt = added.begin(); - std::vector::iterator addedItEnd = added.end(); + std::vector::iterator addedIt = added.begin(); + std::vector::iterator addedItEnd = added.end(); for (IntervalPtrs::iterator i = unhandled_.begin(), e = unhandled_.end(); i != e && addedIt != addedItEnd; ++i) { if ((*i)->start() > (*addedIt)->start()) @@ -399,7 +399,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur) // otherwise we spill all intervals aliasing the register with // minimum weight, rollback to the interval with the earliest // start point and let the linear scan algorithm run again - std::vector added; + std::vector added; assert(MRegisterInfo::isPhysicalRegister(minReg) && "did not choose a register to spill?"); std::vector toSpill(mri_->getNumRegs(), false); @@ -418,7 +418,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur) DEBUG(std::cerr << "\t\t\tspilling(a): " << **i << '\n'); earliestStart = std::min(earliestStart, (*i)->start()); int slot = vrm_->assignVirt2StackSlot((*i)->reg); - std::vector newIs = + std::vector newIs = li_->addIntervalsForSpills(**i, *vrm_, slot); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); @@ -433,7 +433,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur) DEBUG(std::cerr << "\t\t\tspilling(i): " << **i << '\n'); earliestStart = std::min(earliestStart, (*i)->start()); int slot = vrm_->assignVirt2StackSlot((*i)->reg); - std::vector newIs = + std::vector newIs = li_->addIntervalsForSpills(**i, *vrm_, slot); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); @@ -496,10 +496,10 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur) } } - std::sort(added.begin(), added.end(), less_ptr()); + std::sort(added.begin(), added.end(), less_ptr()); // merge added with unhandled - std::vector::iterator addedIt = added.begin(); - std::vector::iterator addedItEnd = added.end(); + std::vector::iterator addedIt = added.begin(); + std::vector::iterator addedItEnd = added.end(); for (IntervalPtrs::iterator i = unhandled_.begin(), e = unhandled_.end(); i != e && addedIt != addedItEnd; ++i) { if ((*i)->start() > (*addedIt)->start()) -- cgit v1.2.3-18-g5258