From d9df5017040489303acb57bdd8697ef0f8bafc08 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Thu, 9 Apr 2009 17:16:43 +0000 Subject: Fix pr3954. The register scavenger asserts for inline assembly with register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/PostRASchedulerList.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/CodeGen/PostRASchedulerList.cpp') diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 311ad28110..f4e958c107 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -500,7 +500,7 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI, if (Reg == 0) continue; if (!MO.isDef()) continue; // Ignore two-addr defs. - if (MI->isRegReDefinedByTwoAddr(i)) continue; + if (MI->isRegTiedToUseOperand(i)) continue; DefIndices[Reg] = Count; KillIndices[Reg] = ~0u; -- cgit v1.2.3-70-g09d2