From 46df4eb46e784036cf895db271fe29e1cf2a975a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 16 Jun 2010 07:35:02 +0000 Subject: Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/PostRAHazardRecognizer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/CodeGen/PostRAHazardRecognizer.cpp') diff --git a/lib/CodeGen/PostRAHazardRecognizer.cpp b/lib/CodeGen/PostRAHazardRecognizer.cpp index 36905466ef..cbde2b01ee 100644 --- a/lib/CodeGen/PostRAHazardRecognizer.cpp +++ b/lib/CodeGen/PostRAHazardRecognizer.cpp @@ -72,7 +72,7 @@ void PostRAHazardRecognizer::ScoreBoard::dump() const { } } -PostRAHazardRecognizer::HazardType +ScheduleHazardRecognizer::HazardType PostRAHazardRecognizer::getHazardType(SUnit *SU) { if (ItinData.isEmpty()) return NoHazard; -- cgit v1.2.3-70-g09d2