From ae3a0be92e33bc716722aa600983fc1535acb122 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 4 Jun 2009 22:49:04 +0000 Subject: Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Bitcode/Reader/BitcodeReader.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'lib/Bitcode/Reader/BitcodeReader.cpp') diff --git a/lib/Bitcode/Reader/BitcodeReader.cpp b/lib/Bitcode/Reader/BitcodeReader.cpp index 1dad04bd8f..3b44f56421 100644 --- a/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/lib/Bitcode/Reader/BitcodeReader.cpp @@ -104,9 +104,12 @@ static int GetDecodedCastOpcode(unsigned Val) { static int GetDecodedBinaryOpcode(unsigned Val, const Type *Ty) { switch (Val) { default: return -1; - case bitc::BINOP_ADD: return Instruction::Add; - case bitc::BINOP_SUB: return Instruction::Sub; - case bitc::BINOP_MUL: return Instruction::Mul; + case bitc::BINOP_ADD: + return Ty->isFPOrFPVector() ? Instruction::FAdd : Instruction::Add; + case bitc::BINOP_SUB: + return Ty->isFPOrFPVector() ? Instruction::FSub : Instruction::Sub; + case bitc::BINOP_MUL: + return Ty->isFPOrFPVector() ? Instruction::FMul : Instruction::Mul; case bitc::BINOP_UDIV: return Instruction::UDiv; case bitc::BINOP_SDIV: return Ty->isFPOrFPVector() ? Instruction::FDiv : Instruction::SDiv; -- cgit v1.2.3-18-g5258