From d70f57b254114841892425a40944268d38ae0bcd Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 19 Jul 2010 22:15:08 +0000 Subject: ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 67ecb72219..926efc4eb7 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -993,6 +993,11 @@ protected: Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; } + /// findRepresentativeClass - Return the largest legal super-reg register class + /// of the specified register class. + virtual const TargetRegisterClass * + findRepresentativeClass(const TargetRegisterClass *RC) const; + /// computeRegisterProperties - Once all of the register classes are added, /// this allows us to compute derived properties we expose. void computeRegisterProperties(); @@ -1698,12 +1703,7 @@ private: /// hasLegalSuperRegRegClasses - Return true if the specified register class /// has one or more super-reg register classes that are legal. - bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC); - - /// findRepresentativeClass - Return the largest legal super-reg register class - /// of the specified register class. - const TargetRegisterClass * - findRepresentativeClass(const TargetRegisterClass *RC); + bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const; }; /// GetReturnInfo - Given an LLVM IR type and return type attributes, -- cgit v1.2.3-70-g09d2