From 14ea1ec2324cb595f2e035bbf54ddcd483f17c11 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 13 Mar 2009 20:42:20 +0000 Subject: Fix FastISel's assumption that i1 values are always zero-extended by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/FastISel.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index 1c26b3fd76..085810aaf1 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -269,6 +269,11 @@ protected: unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, unsigned Op0, uint32_t Idx); + /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op + /// with all but the least significant bit set to zero. + unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT, + unsigned Op); + /// FastEmitBranch - Emit an unconditional branch to the given block, /// unless it is the immediate (fall-through) successor, and update /// the CFG. -- cgit v1.2.3-70-g09d2