From f28987b76e758b5f2fcc2c5d2c8e073df54ca91e Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 15 Jun 2011 23:28:14 +0000 Subject: Use set operations instead of plain lists to enumerate register classes. This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/WritingAnLLVMBackend.html | 80 +++++++++++++++++------------------------- 1 file changed, 33 insertions(+), 47 deletions(-) (limited to 'docs/WritingAnLLVMBackend.html') diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html index 39ac34b3d7..5e3d07067e 100644 --- a/docs/WritingAnLLVMBackend.html +++ b/docs/WritingAnLLVMBackend.html @@ -706,8 +706,7 @@ classes using the following class: 
 class RegisterClass<string namespace,
-list<ValueType> regTypes, int alignment,
-                    list<Register> regList> {
+list<ValueType> regTypes, int alignment, dag regList> {
   string Namespace = namespace;
   list<ValueType> RegTypes = regTypes;
   int Size = 0;  // spill size, in bits; zero lets tblgen pick the size
@@ -717,7 +716,7 @@ list<ValueType> regTypes, int alignment,
   // default value 1 means a single instruction
   // A negative value means copying is extremely expensive or impossible
   int CopyCost = 1;  
-  list<Register> MemberList = regList;
+  dag MemberList = regList;
   
   // for register classes that are subregisters of this class
   list<RegisterClass> SubRegClassList = [];  
@@ -749,9 +748,11 @@ list<ValueType> regTypes, int alignment,
     memory.
 
 
  • The final argument, regList, specifies which registers are in this
-    class.  If an allocation_order_* method is not specified,
-    then regList also defines the order of allocation used by the
-    register allocator.
    • 
+    class. If an alternative allocation order method is not specified, then
+    regList also defines the order of allocation used by the register
+    allocator. Besides simply listing registers with (add R0, R1, ...),
+    more advanced set operators are available. See
+    include/llvm/Target/Target.td for more information.
 
 
 
    
@@ -761,44 +762,31 @@ classes, the first argument defines the namespace with the string
 'SP'. FPRegs defines a group of 32 single-precision
 floating-point registers (F0 to F31); DFPRegs defines
 a group of 16 double-precision registers
-(D0-D15). For IntRegs, the MethodProtos
-and MethodBodies methods are used by TableGen to insert the specified
-code into generated output.
+(D0-D15).
 
    
 
 
    
 
    -def FPRegs : RegisterClass<"SP", [f32], 32,
-  [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
-   F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+// F0, F1, F2, ..., F31
+def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
 
 def DFPRegs : RegisterClass<"SP", [f64], 64,
-  [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>;
+                            (add D0, D1, D2, D3, D4, D5, D6, D7, D8,
+                                 D9, D10, D11, D12, D13, D14, D15)>;
  
 def IntRegs : RegisterClass<"SP", [i32], 32,
-    [L0, L1, L2, L3, L4, L5, L6, L7,
-     I0, I1, I2, I3, I4, I5,
-     O0, O1, O2, O3, O4, O5, O7,
-     G1,
-     // Non-allocatable regs:
-     G2, G3, G4, 
-     O6,        // stack ptr
-    I6,        // frame ptr
-     I7,        // return address
-     G0,        // constant zero
-     G5, G6, G7 // reserved for kernel
-    ]> {
-  let MethodProtos = [{
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    IntRegsClass::iterator
-    IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
-      return end() - 10  // Don't allocate special registers
-         -1;
-    }
-  }];
-}
+    (add L0, L1, L2, L3, L4, L5, L6, L7,
+         I0, I1, I2, I3, I4, I5,
+         O0, O1, O2, O3, O4, O5, O7,
+         G1,
+         // Non-allocatable regs:
+         G2, G3, G4,
+         O6,        // stack ptr
+         I6,        // frame ptr
+         I7,        // return address
+         G0,        // constant zero
+         G5, G6, G7 // reserved for kernel
+    )>;
 
    
 
    
 
@@ -820,10 +808,7 @@ which is included at the bottom of SparcRegisterInfo.cpp, the SPARC
 register implementation. The code below shows only the generated integer
 registers and associated register classes. The order of registers
 in IntRegs reflects the order in the definition of IntRegs in
-the target description file. Take special note of the use
-of MethodBodies in SparcRegisterInfo.td to create code in
-SparcGenRegisterInfo.inc. MethodProtos generates similar code
-in SparcGenRegisterInfo.h.inc.
+the target description file.
 
    
 
 
    
@@ -866,13 +851,7 @@ namespace SP {   // Register class instances
   static const TargetRegisterClass* const IntRegsSuperclasses [] = {
     NULL
   };
-...
-  IntRegsClass::iterator
-  IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
-     return end()-10  // Don't allocate special registers
-         -1;
-  }
-  
+
   IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID, 
     IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses, 
     IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
@@ -880,6 +859,13 @@ namespace SP {   // Register class instances
    +

    +The register allocators will avoid using reserved registers, and callee saved +registers are not used until all the volatile registers have been used. That +is usually good enough, but in some cases it may be necessary to provide custom +allocation orders. +

    + -- cgit v1.2.3-70-g09d2