From 05d0265fef651de152c8127aa701e689555649f3 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 18 Apr 2011 23:59:50 +0000 Subject: docs: Use as Heading elements instead of
. H1 ... doc_title H2 ... doc_section H3 ... doc_subsection H4 ... doc_subsubsection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129736 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/CodeGenerator.html | 303 ++++++++++++++++++++++++------------------------ 1 file changed, 152 insertions(+), 151 deletions(-) (limited to 'docs/CodeGenerator.html') diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 5ca40afc33..50036f2ed7 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -19,9 +19,9 @@ -
+

The LLVM Target-Independent Code Generator -

+
  1. Introduction @@ -127,9 +127,9 @@
-
+

Introduction -

+
@@ -191,9 +191,9 @@
-
+

Required components in the code generator -

+
@@ -223,9 +223,9 @@
-
+

The high-level design of the code generator -

+
@@ -297,9 +297,9 @@
-
+

Using TableGen for target description -

+
@@ -325,9 +325,9 @@
-
+

Target description classes -

+
@@ -349,9 +349,9 @@
-
+

The TargetMachine class -

+
@@ -369,9 +369,9 @@
-
+

The TargetData class -

+
@@ -385,9 +385,9 @@
-
+

The TargetLowering class -

+
@@ -411,9 +411,9 @@
-
+

The TargetRegisterInfo class -

+
@@ -445,9 +445,9 @@
-
+

The TargetInstrInfo class -

+
@@ -463,9 +463,9 @@
-
+

The TargetFrameInfo class -

+
@@ -479,9 +479,9 @@
-
+

The TargetSubtarget class -

+
@@ -495,9 +495,9 @@ -
+

The TargetJITInfo class -

+
@@ -510,9 +510,9 @@
-
+

Machine code description classes -

+
@@ -531,9 +531,9 @@
-
+

The MachineInstr class -

+
@@ -579,9 +579,9 @@
-
+

Using the MachineInstrBuilder.h functions -

+
@@ -630,9 +630,9 @@ MI.addReg(Reg, RegState::Define);
-
+

Fixed (preassigned) registers -

+
@@ -702,9 +702,9 @@ ret
-
+

Machine code in SSA form -

+
@@ -720,9 +720,9 @@ ret
-
+

The MachineBasicBlock class -

+
@@ -737,9 +737,9 @@ ret
-
+

The MachineFunction class -

+
@@ -756,9 +756,9 @@ ret -
+

The "MC" Layer -

+
@@ -783,9 +783,9 @@ in this manual. -
+

The MCStreamer API -

+
@@ -817,9 +817,9 @@ MCObjectStreamer implements a full assembler.
-
+

The MCContext class -

+
@@ -832,9 +832,9 @@ interact with to create symbols and sections. This class can not be subclassed.
-
+

The MCSymbol class -

+
@@ -864,9 +864,9 @@ like this to the .s file:

-
+

The MCSection class -

+
@@ -882,9 +882,9 @@ directive in a .s file).
-
+

The MCInst class -

+
@@ -906,9 +906,9 @@ printer, and the type generated by the assembly parser and disassembler. -
+

Target-independent code generation algorithms -

+
@@ -920,9 +920,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

Instruction Selection -

+
@@ -939,9 +939,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

Introduction to SelectionDAGs -

+
@@ -1001,9 +1001,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

SelectionDAG Instruction Selection Process -

+
@@ -1082,9 +1082,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

Initial SelectionDAG Construction -

+
@@ -1102,9 +1102,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

SelectionDAG LegalizeTypes Phase -

+
@@ -1135,9 +1135,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

SelectionDAG Legalize Phase -

+
@@ -1167,10 +1167,11 @@ printer, and the type generated by the assembly parser and disassembler.
-
- SelectionDAG Optimization Phase: the DAG - Combiner -
+

+ + SelectionDAG Optimization Phase: the DAG Combiner + +

@@ -1202,9 +1203,9 @@ printer, and the type generated by the assembly parser and disassembler.
-
+

SelectionDAG Select Phase -

+
@@ -1363,9 +1364,9 @@ def : Pat<(i32 imm:$imm),
-
+

SelectionDAG Scheduling and Formation Phase -

+
@@ -1384,9 +1385,9 @@ def : Pat<(i32 imm:$imm),
-
+

Future directions for the SelectionDAG -

+
@@ -1399,15 +1400,15 @@ def : Pat<(i32 imm:$imm),
-
+

SSA-based Machine Code Optimizations -

+

To Be Written

-
+

Live Intervals -

+
@@ -1420,9 +1421,9 @@ def : Pat<(i32 imm:$imm),
-
+

Live Variable Analysis -

+
@@ -1466,9 +1467,9 @@ def : Pat<(i32 imm:$imm),
-
+

Live Intervals Analysis -

+
@@ -1486,9 +1487,9 @@ def : Pat<(i32 imm:$imm),
-
+

Register Allocation -

+
@@ -1504,9 +1505,9 @@ def : Pat<(i32 imm:$imm), -
+

How registers are represented in LLVM -

+
@@ -1617,9 +1618,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, -
+

Mapping virtual registers to physical registers -

+
@@ -1667,9 +1668,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
-
+

Handling two address instructions -

+
@@ -1703,9 +1704,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
-
+

The SSA deconstruction phase -

+
@@ -1727,9 +1728,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
-
+

Instruction folding -

+
@@ -1764,9 +1765,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, -
+

Built in register allocators -

+
@@ -1806,20 +1807,20 @@ $ llc -regalloc=pbqp file.bc -o pbqp.s;
-
+

Prolog/Epilog Code Insertion -

+

To Be Written

-
+

Late Machine Code Optimizations -

+

To Be Written

-
+

Code Emission -

+
@@ -1882,9 +1883,9 @@ to implement an assembler for your target.

-
+

Implementing a Native Assembler -

+
@@ -1899,15 +1900,15 @@ compiler.

-
Instruction Parsing
+

Instruction Parsing

To Be Written

-
+

Instruction Alias Processing -

+

Once the instruction is parsed, it enters the MatchInstructionImpl function. @@ -1925,7 +1926,7 @@ description.

-
Mnemonic Aliases
+

Mnemonic Aliases

@@ -1965,7 +1966,7 @@ on the current instruction set.

-
Instruction Aliases
+

Instruction Aliases

@@ -2031,7 +2032,7 @@ subtarget specific.

-
Instruction Matching
+

Instruction Matching

To Be Written

@@ -2039,9 +2040,9 @@ subtarget specific.

-
+

Target-specific Implementation Notes -

+
@@ -2053,9 +2054,9 @@ subtarget specific.

-
+

Target Feature Matrix -

+
@@ -2231,7 +2232,7 @@ is the key:

-
Is Generally Reliable
+

Is Generally Reliable

This box indicates whether the target is considered to be production quality. @@ -2241,7 +2242,7 @@ continuous use.

-
Assembly Parser
+

Assembly Parser

This box indicates whether the target supports parsing target specific .s @@ -2253,7 +2254,7 @@ support in the native .o file writer.

-
Disassembler
+

Disassembler

This box indicates whether the target supports the MCDisassembler API for @@ -2262,7 +2263,7 @@ disassembling machine opcode bytes into MCInst's.

-
Inline Asm
+

Inline Asm

This box indicates whether the target supports most popular inline assembly @@ -2274,7 +2275,7 @@ constraints relating to the X86 floating point stack.

-
JIT Support
+

JIT Support

This box indicates whether the target supports the JIT compiler through @@ -2286,7 +2287,7 @@ in ARM codegen mode, but lacks NEON and full Thumb support.

-
.o File Writing
+

.o File Writing

@@ -2302,7 +2303,7 @@ file to a .o file (as is the case for many C compilers).

-
Tail Calls
+

Tail Calls

@@ -2317,9 +2318,9 @@ more more details.

-
+

Tail call optimization -

+
@@ -2383,9 +2384,9 @@ define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
-
+

Sibling call optimization -

+
@@ -2427,9 +2428,9 @@ entry:
-
+

The X86 backend -

+
@@ -2440,9 +2441,9 @@ entry:
-
+

X86 Target Triples supported -

+
@@ -2469,9 +2470,9 @@ entry:
-
+

X86 Calling Conventions supported -

+
@@ -2489,9 +2490,9 @@ entry:
-
+

Representing X86 addressing modes in MachineInstrs -

+
@@ -2526,9 +2527,9 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
-
+

X86 address spaces supported -

+
@@ -2571,9 +2572,9 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
-
+

Instruction naming -

+
@@ -2592,9 +2593,9 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
-
+

The PowerPC backend -

+
@@ -2605,9 +2606,9 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
-
+

LLVM PowerPC ABI -

+
@@ -2625,9 +2626,9 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
-
+

Frame Layout -

+
@@ -2772,9 +2773,9 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
-
+

Prolog/Epilog -

+
@@ -2789,9 +2790,9 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
-
+

Dynamic Allocation -

+
-- cgit v1.2.3-70-g09d2