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2011-10-16Overhaul the 'test-release' script.Bill Wendling
This removes support for building llvm-gcc. It will eventually add support for building other projects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142165 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Update the tree before applying patch.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 PEXTR and PDEP instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper
VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Make SMDiagnostic a little more sane. Instead of passing around ↵Chris Lattner
note/warning/error as a string, pass it around as an enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner
does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper
3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add a helper script to create branches and tag release candidates.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add a script that helps merge changes into a release branch.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper
because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Fix threads/jobs CalculationDavid Greene
Pass the correct jobs and threads information to the builder. We were underutilizing the number of jobs and threads specified by the user. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add Helpful MessagesDavid Greene
Bit just a bit more verbose about what's going on. Print options to make to aid debugging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add Option to Skip InstallDavid Greene
Add a --no-install option to skip installing components. This speeds up the develop/test cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add Option to Skip gcc BuildDavid Greene
And a --no-gcc option to skip dragonegg and gcc builds. This greatly speeds up the develop/test cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add X86 ANDN instruction. Including instruction selection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Ban rematerializable instructions with side effects.Jakob Stoklund Olesen
TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Remove extra semicolon.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper
for 64BIT_REXW_XD not existing, but it does exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen
This should unbreak the picky buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen
The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Remove MultidefsDavid Greene
Multidefs are a bit unwieldy and incomplete. Remove them in favor of another mechanism, probably for loops. Revert "Make Test More Thorough" Revert "Fix a typo." Revert "Vim Support for Multidefs" Revert "Emacs Support for Multidefs" Revert "Document Multidefs" Revert "Add a Multidef Test" Revert "Update Test for Multidefs" Revert "Process Multidefs" Revert "Parser Multidef Support" Revert "Lexer Support for Multidefs" Revert "Add Multidef Data Structures" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper
64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the Clang tblgen backends from LLVM.Peter Collingbourne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper
was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Build system infrastructure for multiple tblgens.Peter Collingbourne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the TRI::getSubRegisterRegClass() hook.Jakob Stoklund Olesen
This restores my karma after I added TRI::getSubClassWithSubReg(). Register constraints are applied 'backwards'. Starting from the register class required by an instruction operand, the correct question is: 'How can I constrain the super-register register class so all its sub-registers satisfy the instruction constraint?' The getMatchingSuperRegClass() hook answers that. We never need to go 'forwards': Starting from a super-register register class, what register class are the sub-registers in? The getSubRegisterRegClass() hook did that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Vim Support for MultidefsDavid Greene
Add vim highlighting support for multidefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Emacs Support for MultidefsDavid Greene
Add Emacs font-lock keyword support for multidefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen
This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Properly use const_iterator.Jakob Stoklund Olesen
This should unbreak the Windows build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Teach TableGen to infer missing register classes.Jakob Stoklund Olesen
The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Store all allocation orders together.Jakob Stoklund Olesen
There is no need to keep the primary order separate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen
When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen
The RecordKeeper could be shared by multiple target instances, causing duplicate record errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper
instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Remove last references to hotpatch.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Find the strip tool that works with the specified SDKROOT. rdar://10165908Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02Fix typo in r140954.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper
0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne
This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Subtarget getFeatureBits() returns a uint64_t, not unsigned.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().Jakob Stoklund Olesen
All the sub-class bit vectors are computed when first creating the register bank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Store sub-class lists as a bit vector.Jakob Stoklund Olesen
This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Extract a slightly more general BitVector printer.Jakob Stoklund Olesen
This one can also print 32-bit groups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen
Use these lists instead of computing them on the fly in RegisterInfoEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Implement VarListElementInit:: resolveListElementReferenceDavid Greene
Implement VarListElementInit:: resolveListElementReference so that lists of lists can be indexed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140882 91177308-0d34-0410-b5e6-96231b3b80d8
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