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2011-04-21Don't allow per-register spill size and alignment.Jakob Stoklund Olesen
These values were not used for anything. Spill size and alignment is a property of the register class, not the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Invert the meaning of printAliasInstr's return value. It now returnsEric Christopher
true on success and false on failure. Update callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Enhance the fixed-length disassembler to support the callbacks necessary for ↵Owen Anderson
symbolic disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner
the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Implement major new fastisel functionality: the matcher can now handle ↵Chris Lattner
immediates with value constraints on them (when defined as ImmLeaf's). This is particularly important for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand, which has a value constraint. Before this patch we ended up iseling the examples into such amazing code as: movabsq $7, %rax imulq %rax, %rdi movq %rdi, %rax ret now we produce: imulq $7, %rdi, %rax ret This dramatically shrinks the generated code at -O0 on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17introduce a new OpKind abstraction which wraps up operand flavors in a tidy ↵Chris Lattner
little wrapper. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17change OperandsSignature to use SmallVector<char> instead of std::vector<string>Chris Lattner
since the strings are always exactly one character, and there are usually only 2-3 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17since the VT is fixed for a ImmLeaf, there is no reason to expose it to the ↵Chris Lattner
matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner
kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17Rework our internal representation of node predicates to expose moreChris Lattner
structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17remove some debugging code I added.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-171. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner
2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Initial work to improve documentation for Clang's diagnostics, from Matthieu ↵Douglas Gregor
Monrocq git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129613 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some ↵Evan Cheng
targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13Add an option to not print the alias of an instruction. It defaults to "printBill Wendling
the alias". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen
rdar://problem/9267838 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11TableGen: Keep the order of DECL_CONTEXT() for DeclNodes.td. RecordVector ↵NAKAMURA Takumi
may be used instead of RecordSet. The result of DeclNodes.inc was unstable on msys, Windows 7 x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11build: Add support for a SHOW_DIAGNOSTICS build variable.Daniel Dunbar
If enabled, this will attempt to use the CC_LOG_DIAGNOSTICS feature I dropped into Clang to print a log of all the diagnostics generated during an individual build (from the top-level). Not sure if this will actually be useful, but for now it is handy for testing the option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129312 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09fix PR9629 - We were lowering regexes like a{{b|c}}d into ab|cd, whichChris Lattner
is substantially different than a(b|c)d. Form the latter regex instead. This found a few problems in the testsuite, which serves as its test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09various cleanups, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Only emit the AvailableFeatures variable if it's used.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling
with the newer, cleaner model. It uses the IAPrinter class to hold the information that is needed to match an instruction with its alias. This also takes into account the available features of the platform. There is one bit of ugliness. The way the logic determines if a pattern is unique is O(N**2), which is gross. But in reality, the number of items it's checking against isn't large. So while it's N**2, it shouldn't be a massive time sink. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Add support for the VIA PadLock instructions.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Use array_lengthofJoerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Change loops to derive the number of tables automaticallyJoerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Add annotations to tablegen-generated processor itineraries, or replace them ↵Andrew Trick
with something meaningful. I want to be able to read and debug the generated tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Fix typo in generated HTML.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Use intrinsics for Neon vmull operations. Radar 9208957.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30ClangSAEmClangSACheckersEmitter, emit info about groups.Argyrios Kyrtzidis
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29Quiet a gcc warning about changed name lookup rulesMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29In ClangSACheckersEmitter:Argyrios Kyrtzidis
- Also emit a list of packages and groups sorted by name - Avoid iterating over DenseSet so that the output of the arrays is deterministic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29For ClangSACheckersEmitter, allow a package to belong to checker group, in ↵Argyrios Kyrtzidis
which all its checkers will go into the group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28Remove scripts used by TEST=dbg from here. They now live inside llvm test suite.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-27Partially revert commit 127155: I think it is much more convenientDuncan Sands
to have structured log files rather than one big file produced by piping output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26Extend Clang's TableGen emitter for attributes to support bool arguments.Douglas Gregor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25Useful script for finding regressions in the nightly testsuite.Duncan Sands
I think it was written by Pawel Worach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen
instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen
stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen
was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23Update the Clang attribute emitter to handle attributes of 'version'Douglas Gregor
kind, and fix serialization/deserialization of IdentifierInfo attributes. These are requires for the new 'availability' attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Call static functions so that they aren't left unused.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128020 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21A WIP commit of the InstAlias printing cleanup. This code will soon replace theBill Wendling
code below it. Even though it looks very similar, it will match more precisely and geneate better functions in the long run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Add the IAPrinter class.Bill Wendling
This is a helper class that will make it easier to say which InstAliases can be printed and which cannot (because of ambiguity). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21* Add classes that support the "feature" information.Bill Wendling
* Move the code that emits the reg in reg class matching into its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127988 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 06:17:42 +0000