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2013-04-11Add CLAC/STAC instruction encoding/decoding supportMichael Liao
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Don't descend into .git directories during test discovery.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Shorten a metavar to make --help look nicer.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Add a test for discovery when exact test names are given.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11lit: Add a trivial test of the basic progress bar.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Move yaml2obj to tools too.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Use ScalarBitSetTraits.Rafael Espindola
What was missing was were the type strong operator|. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178879 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Move obj2yaml to tools to sort out make's dependencies.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Build obj2yaml with configure+make.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Add back parsing of header charactestics.Rafael Espindola
It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove anonymous namespace.Rafael Espindola
Looks like the gcc in http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32/ doesn't like "not external linkage": /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h: In instantiation of 'const bool llvm::yaml::has_SequenceMethodTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::value': /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:281: instantiated from 'llvm::yaml::has_SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >' /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/utils/yaml2obj/yaml2obj.cpp:627: instantiated from here /Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:243: error: 'llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size' is not a valid template argument for type 'size_t (*)(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' because function 'static size_t llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' has not external linkage git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Use yaml::IO in yaml2obj.cpp.Rafael Espindola
The generic structs and specializations will be refactored when obj2yaml is changed to use yaml::IO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Fix TableGen subtarget-emitter to handle A9/Swift.Andrew Trick
A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Revert r178166. According to Howard, this code is actually ok.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Avoid undefined behavior from passing a std::vector's own contentsDan Gohman
in as an argument to push_back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick
Allow variants to be defined only for some processors on a target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- add the XTEST instructionDave Zarzycki
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow types to be omitted in output patterns.Jakob Stoklund Olesen
This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen
This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Allow direct value types in pattern definitions.Jakob Stoklund Olesen
Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen
A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Plug a memory leak in FileCheck when the input file is empty.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Add TableGen ctags(1) emitter and helper script.Sean Silva
To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20[lit] Avoid CRLFs in bash scripts on WindowsReid Kleckner
Native Windows Python will do line ending translation by default, which we don't want in bash scripts. If we're not native Windows Python, then 'b' is ignored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177602 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Extend TableGen instruction selection matcher to improve handlingUlrich Weigand
of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18TableGen fix for the new machine model.Andrew Trick
Properly handle cases where a group of instructions have different SchedRW lists with the same itinerary class. This was supposed to work, but I left in an early break. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Extract a method.Jakob Stoklund Olesen
This computes the type of an instruction operand or result based on the records in the instruction's ins and outs lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen
Not passing vector references around makes it possible to use SmallVector in most places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick
We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Add SchedRW as an Instruction field.Jakob Stoklund Olesen
Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix r177112: Add ProcResGroup.Andrew Trick
This is the other half of r177122 that I meant to commit at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14MachineModel: Add a ProcResGroup class.Andrew Trick
This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13lit.TestFormats.GoogleTest: Honor LitConfig.noExecute, or --no-execute were ↵NAKAMURA Takumi
ignored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176930 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby
rdar://13318048 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01MIsched machine model: tablegen subtarget emitter improvement.Andrew Trick
Fix the way resources are counted. I'm taking some time to cleanup the way MachineScheduler handles in-order machine resources. Eventually we'll need more PPC/Atom test cases in tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28Enable syntax highlighting for reStructuredText files.Bill Wendling
Patch by Journeyer J. Joh! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-26[TableGen] Fix ICE on MSVC 2012 Release builds.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-26Unify clang/llvm attributes for asan/tsan/msan (LLVM part)Kostya Serebryany
These are two related changes (one in llvm, one in clang). LLVM: - rename address_safety => sanitize_address (the enum value is the same, so we preserve binary compatibility with old bitcode) - rename thread_safety => sanitize_thread - rename no_uninitialized_checks -> sanitize_memory CLANG: - add __attribute__((no_sanitize_address)) as a synonym for __attribute__((no_address_safety_analysis)) - add __attribute__((no_sanitize_thread)) - add __attribute__((no_sanitize_memory)) for S in address thread memory If -fsanitize=S is present and __attribute__((no_sanitize_S)) is not set llvm attribute sanitize_S git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176075 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25'Hexadecimal' has two 'a's and only one 'i'.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176031 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fix for bug 15246 -- out-of-bound error in the TableGen backend, ↵Jyotsna Verma
CodeGenMapTable.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto
Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Add static cast to unsigned char whenever a character classification ↵Guy Benyei
function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo
Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11[tsan/msan] adding thread_safety and uninitialized_checks attributesKostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174864 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07[lit] Add a display function for lit.Test.TestResult.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Canonicalize line endings to Linux style also when the --strict-whitespace ↵Guy Benyei
flag is in use. This flag is supposed to affect horizontal whitespaces only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Allow targets to add custom asm operand matching logic.Jim Grosbach
For example, ARM has several instructions with a literal '#0' immediate in the syntax that's not represented as an actual operand. The asm matcher is expected a token operand, but the parser will have created an immediate operand. This is currently handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but will be better handled by this hook. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Preprocess Apple llvmCore headers to reflect NDEBUG setting. <rdar://12568983>Bob Wilson
If an Apple llvmCore build is done without assertions, and a client uses the llvmCore headers with assertions enabled, or vice versa, then things will break because some of the structure sizes in the API are different. Use the unifdef tool to make the headers unconditionally match the way the llvmCore libraries were built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Set the deployment target for Apple llvmCore builds. <rdar://problem/12712431>Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Fix commentsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
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