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2011-07-14Change Intrinsic::getDeclaration and friends to take an ArrayRef.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson
an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13struct Init -> class InitDavid Greene
Rename struct Init to class Init for consistency and in preparation for making Init a FoldingSetNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Range checking for CDP[2] immediates.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Give the ARM BKPT instruction the right operand type.Jim Grosbach
The immediate is of limited range and the operand type should reflect that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher
in multiple buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Use get(0 Instead of Create()David Greene
Respond to some feedback asking for a name change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11struct Init -> class Init.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Fix BuildDavid Greene
Update the tag for Init to match how it's defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11[AVX] Make Inits FoldableDavid Greene
Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Resynchronize EDInfo.h and EDEmitter.cpp.Shantonu Sen
The enum names as well as order (i.e. value) had skewed, which means that consumers of the tablegen-ed table would see different values than intended. Make both files have a superset of enums, and add classification as needed for numMCOperands. Reviewed by Owen Anderson git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Fix dangling pointer.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Fix a dangling reference. Patch by Dave Abrahams. pr10311Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08TableGen'erated MC lowering for simple pseudo-instructions.Jim Grosbach
This allows the (many) pseudo-instructions we have that map onto a single real instruction to have their expansion during MC lowering handled automatically instead of the current cumbersome manual expansion required. These sorts of pseudos are common when an instruction is used in situations that require different MachineInstr flags (isTerminator, isBranch, et. al.) than the generic instruction description has. For example, using a move to the PC to implement a branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Eliminate asm parser's dependency on TargetMachine:Evan Cheng
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Add isCodeGenOnly value to the CodeGenInstruction class.Jim Grosbach
So users of a CGI don't have to look up the value directly from the original Record; just like the rest of the convenience values in the class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06Typo.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06Don't require pseudo-instructions to carry encoding information.Jim Grosbach
For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01- Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng
itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach
It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach
It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29ARM RSCS* don't need explicit TableGen decoder checks.Jim Grosbach
They've been pseudos for a while now, so the decoder will never see them in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach
The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Change AsmName's type from StringRef to std::string. AsmName was pointing to ↵Francois Pichet
a temporary string object that was destroyed. This is undefined behavior and MSVC didn't like it. This fixes over 300+ failing tests on MSVC. Credit for this fix goes to chapuni. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng
MCInstrItineraries) into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Add MCInstrInfo registeration machinery.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Alternative name enum should go into the enum portion.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM Assembly support for Thumb mov-immediate.Jim Grosbach
Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Remove RCBarriers from TargetInstrDesc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Add support for alternative register names, useful for instructions whose ↵Owen Anderson
operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. MC doesn't need know about subreg indices.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng
into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Remove dead typedefs.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Rename TargetRegisterDesc to MCRegisterDescEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."Bob Wilson
Sorry, this was a bad idea. Within clang these builtins are in a separate "ARM" namespace, but the actual builtin names should clearly distinguish that they are target specific. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Shorten some ARM builtin names by removing unnecessary "neon" prefix.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24- Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng
routines. - Rename TargetRegisterDesc to MCRegisterDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Make the generated InitXXXMCRegisterInfo function "static inline", so it ↵Benjamin Kramer
doesn't get emitted into multiple object files. This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen into a single binary (for example when building a monolithic libLLVM shared library). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
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