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2011-12-15Synthesize missing register class intersections.Jakob Stoklund Olesen
The function TRI::getCommonSubClass(A, B) returns the largest common sub-class of the register classes A and B. This patch teaches TableGen to synthesize sub-classes such that the answer is always maximal. In other words, every register that is in both A and B will also be present in getCommonSubClass(A, B). This introduces these synthetic register classes: ARM: GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR tGPR_and_tcGPR hGPR_and_tcGPR X86: GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR64_NOSP_and_GR64_TC GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_TC GR32_NOAX_and_GR32_NOSP GR64_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_ABCD_and_GR32_NOAX GR64_ABCD_and_GR64_TC GR32_NOAX_and_GR32_TC GR32_AD_and_GR32_NOAX Other targets are unaffected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12Extract a method.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146374 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07ARM: NEON SHLL instruction immediate operand range checking.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Extend AsmMatcher token literal matching to allow aliasing.Jim Grosbach
For example, ARM allows: vmov.u32 s4, #0 -> vmov.i32, #0 'u32' is a more specific designator for the 32-bit integer type specifier and is legal for any instruction which accepts 'i32' as a datatype suffix. We want to say, def : TokenAlias<".u32", ".i32">; This works by marking the match class of 'From' as a subclass of the match class of 'To'. rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06First chunk of MachineInstr bundle support.Evan Cheng
1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Tidy up. Fix naming convention stuff for some internal functions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06use space star instead of star spaceSebastian Pop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06add missing point at the end of sentencesSebastian Pop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02ARM NEON VEXT aliases for data type suffices.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01TableGen: fix CMake build s'moreDylan Noblesmith
Oops, missed another missing file from r145629. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01Add a deterministic finite automaton based packetizer for VLIW architecturesAnshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30Replace an assert() with an actual diagnostic.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30llvm_unreachable() is not for user diagnostics....Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19Remove some unnecessary filtering checks from X86 disassembler table build.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng
integer variants. rdar://10437054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Tidy up. Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11LLVMBuild: Alphabetize required_libraries lists.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10Remove this from the CMake build since I erased the file.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09Remove the old-style ARM disassembler, which is no longer used.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06More AVX2 instructions and their intrinsics.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-03build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02The TableGen parts of the CMake build are seriously broken. This fixesChandler Carruth
one aspect of them by having them use the (annoying, if not broken) proper library dependency model for adding the LLVMTableGen library as a dependency. This could manifest as a link order issue in the presence of separate LLVM / Clang source builds with CMake and a linker that really cares about such things. Also, add the Support dependency to llvm-tblgen itself so that it doesn't rely on TableGen's transitive Support dependency. A parallel change for clang-tblgen will be forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28Allow InstAlias's to use immediate matcher patterns that xform the value.Jim Grosbach
For example, On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a matcher pattern that handles the bitwise negation when mapping to t2MVNi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28Allow register classes to match a containing class in InstAliases.Jim Grosbach
If the register class in the source alias is a subclass of the register class of the actual instruction, the alias can still match OK since the constraints are strictly a subset of what the instruction can actually handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27Delete dead code. Nothing ever instantiates this.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23Add X86 RORX instructionCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer
correctness along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 4-register variant of VLD1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 3-register variant of VLD1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21ARM VLD parsing and encoding.Jim Grosbach
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach
NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Fix unused variable warning in the rare circumstance that we have no ↵Owen Anderson
feature-dependent instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Pick low-hanging MatchEntry shrinkage fruit.Benjamin Kramer
Shaves 200k off Release-Asserts clang binaries on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 PEXTR and PDEP instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper
VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper
3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper
because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add X86 ANDN instruction. Including instruction selection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Ban rematerializable instructions with side effects.Jakob Stoklund Olesen
TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
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