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2012-05-16Significantly reduce the compiled size of Functions.cpp by turning a big ↵Chris Lattner
blob of tblgen generated code (for Intrinsic::getType) into a table. This handles common cases right now, but I plan to extend it to handle all cases and merge in type verification logic as well in follow-on patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156905 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16have tblgen emit cast<> instead of dyn_cast<> when we know it must succeed.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15TableGen'erate mapping physical registers to encoding values.Jim Grosbach
Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Create a struct representing register units in TableGen.Jakob Stoklund Olesen
Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen
Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen
The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Compute topological signatures of registers.Jakob Stoklund Olesen
TableGen creates new register classes and sub-register indices based on the sub-register structure present in the register bank. So far, it has been doing that on a per-register basis, but that is not very efficient. This patch teaches TableGen to compute topological signatures for registers, and use that to reduce the amount of redundant computation. Registers get the same TopoSig if they have identical sub-register structure. TopoSigs are not currently exposed outside TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12Speed up computeComposites() by using the new SubReg -> SubIdx map.Jakob Stoklund Olesen
TableGen doesn't need to search through the SubRegs map to find an inverse entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Remove extraneous ; and the resulting warning.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Defer computation of SuperRegs.Jakob Stoklund Olesen
Don't compute the SuperRegs list until the sub-register graph is completely finished. This guarantees that the list of super-registers is properly topologically ordered, and has no duplicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Compute secondary sub-registers.Jakob Stoklund Olesen
The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen
The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick
I initially assumed that the subreg graph was a tree. That may not be true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Fix warning text.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen
This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen
That's what it does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06TableGen: AsmMatcher diagnostic when missing instruction mnemonic.Jim Grosbach
Previously, if an instruction definition was missing the mnemonic, the next line would just assert(). Issue a real diagnostic instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Order register classes by spill size first, members last.Jakob Stoklund Olesen
This is still a topological ordering such that every register class gets a smaller enum value than its sub-classes. Placing the smaller spill sizes first makes a difference for the super-register class bit masks. When looking for a super-register class, we usually want the smallest possible kind of super-register. That is now available as the first bit set in the bit mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen
This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen
TargetRegisterClass now gives access to the necessary tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen
This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Emit SuperRegMasks as part of the existing SubClassMask arrays.Jakob Stoklund Olesen
The RC->getSubClassMask() pointer now points to a sequence of register class bit masks. The first bit mask is the normal sub-class mask. The following masks are super-reg class masks used by getMatchingSuperRegClass(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen
Many register classes only have a few super-registers, so it is not necessary to keep individual bit masks for all possible sub-register indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen
Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor
be used by clang-tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper
only targets that want the function get it. This prevents other targets from getting an unused function warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach
When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-21Remove 'XXXRegisterClass' from tablegen output. Targets should use ↵Craig Topper
'&XXXRegClass' instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20TableGen'd RegPressure: Added getPressureSetName.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19TableGen support for auto-generating assembly two-operand aliases.Jim Grosbach
Assembly matchers for instructions with a two-operand form. ARM is full of these, for example: add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted. The property TwoOperandAliasConstraint on the instruction definition controls when, and if, an alias will be formed. No explicit InstAlias definitions are required. rdar://11255754 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19Use a SmallVector instead of std::vector for ResOperands.Jim Grosbach
There's almost always a small number of instruction operands, so use a SmallVector and save on heap allocations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19Update some internal naming conventions to modern style.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-19Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a ↵Craig Topper
functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Fix typo.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Revert "Replace some uses of std:map<std::string,...> with StringMap."Jim Grosbach
StringMap iterators are not deterministic, and that's more important here than speed or memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18tblgen: remove duplicated newlines.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Replace some uses of std:map<std::string,...> with StringMap.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Use SmallVector for the requirements on an InstAlias.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Tidy up. Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Move a few more warnings to use PrintWarning().Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Tidy up. No need for a Twine here, as it's just constants.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Tidy up. Add a '.' at the end of the sentence.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Clean up warning text. Remove extraneous prefix.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155015 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18TableGen use PrintWarning rather than fprintf(stderr,...) for warnings.Jim Grosbach
That way we get source line number information from the diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga
coprocessor number was removed for this instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Sanity check error handling for TokenAlias.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Tidy up. 80 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-13Fix target specific intrinsic handling to adjust intrinsic number before ↵Craig Topper
doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Remove incorrect comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154533 91177308-0d34-0410-b5e6-96231b3b80d8
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