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2012-07-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07Tweak spelling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Fix the C++11 build. I hate narrowing conversions.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Fix Windows build after r159281: s/iterator/const_iteratorAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Silence unused variable warning.Richard Trieu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Refactor and speed up DFA generator.Anshuman Dasgupta
Patch by Ivan Llopard! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26TableGen: AsmMatcher diagnostics preference detail.Jim Grosbach
Don't override a custom diagnostic w/ a generic InvalidOperand, all else being equal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159238 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26X86: add GATHER intrinsics (AVX2) in LLVMManman Ren
Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Teach TableGen to put chains on more instructionsTim Northover
When generating selection tables for Pat instances, TableGen relied on an output Instruction's Pattern field being set to infer whether a chain should be added. This patch adds additional logic to check various flag fields so that correct code can be generated even if Pattern is unset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159217 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22TableGen: AsmMatcher support for better operand diagnostics.Jim Grosbach
"Invalid operand" may be a completely correct diagnostic, but it's often insufficiently specific to really help identify and fix the problem in assembly source. Allow a target to specify a more-specific diagnostic kind for each AsmOperandClass derived definition and use that to provide more detailed diagnostics when an operant of that class resulted in a match failure. rdar://8987109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel
Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Use "NoItineraries" for processors with no itineraries.Andrew Trick
This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18Allow up to 64 functional units per processor itinerary.Hal Finkel
This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158679 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18TableGen: AsmMatcher missing-features list minimization.Jim Grosbach
When returning a 'cannot match due to missing CPU features' error code, if there are multiple potential matches with different feature sets, return the smallest set of missing features from the alternatives as that's most likely to be the one that's desired. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Add two newlines in ParseSubtargetFeatures's debug output after the CPU is ↵Hal Finkel
printed. There is otherwise not a newline between the CPU name and the start of the next pass's output which makes both difficult to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen
The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Sched itinerary fix: Avoid static initializers.Andrew Trick
This fixes an accidental dependence on static initialization order that I introduced yesterday. Thank you Lang!!! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a ↵Owen Anderson
complex operand are called out explicitly in the asm string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Round 2 of dead private variable removal.Benjamin Kramer
LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: Added MultiIssueItineraries.Andrew Trick
This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Didn't mean to export this function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Emit register unit root tables.Jakob Stoklund Olesen
Each register unit has one or two root registers. The full set of registers containing a given register unit can be computed as the union of the root registers and their super-registers. Provide an MCRegUnitRootIterator class to enumerate the roots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Print uint16_t numbers without a sign.Jakob Stoklund Olesen
It seems I broke C++11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Remove little semicolon that caused a lot of warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Emit register unit lists for each register.Jakob Stoklund Olesen
Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer
extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28switch AttrListPtr::get to take an ArrayRef, simplifying a lot of clients.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27rdar://11542750 - llvm.trap should be marked no return.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27Reimplement the intrinsic verifier to use the same table as ↵Chris Lattner
Intrinsic::getDefinition, making it stronger and more sane. Delete the code from tblgen that produced the old code. Besides being a path forward in intrinsic sanity, this also eliminates a bunch of machine generated code that was compiled into Function.o git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27move some code around so that Verifier.cpp can get access to the intrinsic ↵Chris Lattner
info table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27enhance the intrinsic info table to encode what *kind* of Any argumentChris Lattner
it is (at the cost of 45 bytes of extra table space) so that the verifier can start using it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-26rearrange some code, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25Compress MCRegisterInfo register name tables.Jakob Stoklund Olesen
Store (debugging) register names as offsets into a string table instead of as char pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157449 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24Teach tblgen's set theory "sequence" operator to support an optional stride ↵Owen Anderson
operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23Fixed typo in r156905.Patrik Hägglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23small refinement to r157218 to save a tiny amount of table size in the commonChris Lattner
case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-22Also compute TopoSigs in synthetic register classes.Jakob Stoklund Olesen
CodeGenRegisterClass has two constructors. Both need to compute the TopoSigs BitVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-21Added address space qualifier to intrinsic PointerType arguments.Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits ↵Chris Lattner
into a separate side table, using the handy SequenceToOffsetTable class. This encodes all these weird things into another 256 bytes, allowing all intrinsics to be encoded this way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17finish encoding all of the interesting details of intrinsics. Now intrinsicsChris Lattner
are only rejected because they can't be encoded into a 32-bit unit, not because they contain an unencodable feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17strengthen the intrinsic descriptor stuff to be able to handle sin, cos and ↵Chris Lattner
other intrinsics that use passed-in arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156977 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17simplify code generated by tblgen that is not necessary since we droppedChris Lattner
compatibility with LLVM 2.x bitcode files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17I forgot the #ifdef _MSC_VER guard in my last commit.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156975 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17Fix the MSVC 2010 build: disable the optimizer for a problematic function.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen
TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
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