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2013-01-09Check whether MCInst operand isImm before calling getImm.Tim Northover
When processing possible aliases, TableGen assumes that if an operand *can* be an immediate, then it always *will* be. This is incorrect for the AArch64 backend. This patch inserts a check in the generated code to make sure isImm is true first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09MIsched: add an ILP window property to machine model.Andrew Trick
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02Sort a few more #include lines in tools/... unittests/... and utils/...Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in ↵NAKAMURA Takumi
fieldFromInstruction(). Reported by Yang Yongyong, thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of ↵Bill Wendling
attribute instead of the value of the attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Fix an uninitialized member variable, found by -fsanitize=bool.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach
MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling
single attribute in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Fix PR14568: Avoid the DFA packetizer from making an invalid readAnshuman Dasgupta
beyond array bounds. No test case since I cannot reproduce an ICE with this bug. According to Carlos -- the bug reporter -- a segfault occurs only when LLVM is compiled with a specific version of GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07s/AttrListPtr/AttributeSet/g to better label what this class is going to be ↵Bill Wendling
in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegisterPresssureTracker: Track live physical register by unit.Andrew Trick
This is much simpler to reason about, more efficient, and fixes some corner cases involving implicit super-register defs. Fixed rdar://12797931. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegisterPressure API. Add support for physical register units.Andrew Trick
At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Copy clang/Driver/<Option parsing stuff> to llvm.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Sort the #include lines for utils/...Chandler Carruth
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen
Use this type for arrays of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen
This class has been merged into its super-class TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20Make the AttrListPtr object a part of the LLVMContext.Bill Wendling
When code deletes the context, the AttributeImpls that the AttrListPtr points to are now invalid. Therefore, instead of keeping a separate managed static for the AttrListPtrs that's reference counted, move it into the LLVMContext and delete it when deleting the AttributeImpls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao
This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Fix issue with invalid flat operand numberEvandro Menezes
Avoid iterating over list of operands beyond the number of operands in it. PS: this fixes issue with revision #167634. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Fix issue with invalid flat operand numberEvandro Menezes
Avoid iterating over list of operands beyond the number of operands in it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08Add support of RTM from TSX extensionMichael Liao
- Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-02Fix a build problem with xlc. The error message wasRafael Espindola
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+". "../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate. Patch by Kai. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Generate a table-driven version of TRI::composeSubRegIndices().Jakob Stoklund Olesen
Explicitly allow composition of null sub-register indices, and handle that common case in an inlinable stub. Use a compressed table implementation instead of the previous nested switches which generated pretty bad code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Don't return false when the function's return type is a pointer.Kaelyn Uhrain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Remove unused member & unnecessary semicolon.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25llvm/utils/TableGen/CMakeLists.txt: Update corresponding to r166685.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25add TableGen support to create relationship maps between instructionsSebastian Pop
Relationship maps are represented as InstrMapping records which are parsed by TableGen and the information is used to construct mapping tables to represent appropriate relations between instructions. These tables are emitted into XXXGenInstrInfo.inc file along with the functions to query them. Patch by Jyotsna Verma <jverma@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Don't use stack unwinding to provide the location information forJoerg Sonnenberger
SetTheory, but pass down the location explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-20Allow the commuted form of tied-operand constraints in tablegen ("$dst = $src",Lang Hames
rather than "$src = $dst"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Add an enum for the return and function indexes into the AttrListPtr object. ↵Bill Wendling
This gets rid of some magic numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Attributes RewriteBill Wendling
Convert the internal representation of the Attributes class into a pointer to an opaque object that's uniqued by and stored in the LLVMContext object. The Attributes class then becomes a thin wrapper around this opaque object. Eventually, the internal representation will be expanded to include attributes that represent code generation options, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12[ms-inline asm] Use the new API introduced in r165830 in lieu of theChad Rosier
MapAndConstraints vector. Also remove the unused Kind argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Change (!list.size() == 0) to (!list.empty()). No functional change.Richard Trieu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165812 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Remove unnecessary classof()'sSean Silva
isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Remove extra semicolons.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Compile TableGen without RTTI.Sean Silva
TableGen no longer needs RTTI! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Move mini Type hierarchy to LLVM-style RTTI.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Use semantically correct RTTI functions.Sean Silva
Also, some minor cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Pass into the AttributeWithIndex::get method an ArrayRef of attributeBill Wendling
enums. These are then created via the correct Attributes creation method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10TableGen subtarget emitter cleanup.Andrew Trick
Consistently evaluate Aliases and Sequences recursively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: Generate IsBuffered flag for machine resources.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165403 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05[ms-inline asm] Add a few typedefs to simplify future changes.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.Sean Silva
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of these uses are actually more like isa<> or cast<>, and will be changed to the semanticaly appropriate one in a future patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Added instregex support to TableGen subtarget emitter.Andrew Trick
This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick
A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
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