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path: root/utils/TableGen/RegisterInfoEmitter.cpp
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2010-12-14Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of allJakob Stoklund Olesen
registers that alias Reg, including itself. This is almost the same as the existing getAliasSet() method, except for the inclusion of Reg. The name matches the reflexive TRI::regsOverlap(x, y) relation. It is very common to do stuff to a register and all its aliases: stuff(Reg) for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) stuff(*Alias); That can now be written as the simpler: for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) stuff(*Alias); This change requires a bit more constant space for the alias lists because Reg is included and because the empty alias list cannot be shared any longer. If the getAliasSet method is eventually removed, this space can be reclaimed by sharing overlap lists. For instance, %rax and %eax have identical overlap sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13eliminate the Records global variable, patch by Garrison Venn!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Split out register class subclassing to a separate function and clean upEric Christopher
accordingly. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman
MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28Emit TargetRegisterInfo::composeSubRegIndices().Jakob Stoklund Olesen
Also verify that all subregister indices compose unambiguously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Check that inherited subregisters all have a direct SubRegIndex.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Suppress emmission of empty subreg/superreg/alias sets.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen
A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen
This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen
A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen
instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen
structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Add the SubRegIndex TableGen class.Jakob Stoklund Olesen
This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Remove unneeded ';' and a class/struct mismatch (noticed by clang).Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to ↵Evan Cheng
replace broken code in VirtRegRewriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88753 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-13eliminate the TargetRegisterDesc::AsmName field, the asmprinters now have ↵Chris Lattner
this table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson
while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson
own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-30Minor whitespace tidiness.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar
- Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30Slightly change TableGen's definition of a register subclass.Jakob Stoklund Olesen
A subclass is allowed to have a larger spill size than the superclass, and the spill alignment must be a multiple of the superclass alignment. This causes the following new subclass relations: === Alpha === F4RC -> F8RC === PPC === F4RC -> F8RC === SPU === R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG === X86 === FR32 -> FR64 -> VR128 RFP32 -> RFP64 -> RFP80 These subclass relations are consistent with the behaviour of -join-cross-class-copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70511 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09Give register alias checking the hash table treatment too.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09Convert TargetRegisterInfo's super-register checking to use a pre-computed ↵Owen Anderson
hash table just like subregister checking does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03"This adds a getName() method to TargetRegisterClass, just like in ↵Chris Lattner
TargetRegisterInfo. This makes debugging register classes a bit easier." Patch by Jakob Stoklund Olesen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68400 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-22Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and ↵Evan Cheng
SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17Fun x86 encoding tricks: when adding an immediate value of 128,Dan Gohman
use a SUB instruction instead of an ADD, because -128 can be encoded in an 8-bit signed immediate field, while +128 can't be. This avoids the need for a 32-bit immediate field in this case. A similar optimization applies to 64-bit adds with 0x80000000, with the 32-bit signed immediate field. To support this, teach tablegen how to handle 64-bit constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-11Indentation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-11Change getSubReg semantics. It now returns zero if the specified register ↵Evan Cheng
doesn't have a subreg of the specified index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56099 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-08Fix typos in (generated) comments.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55916 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26- small bug corrected: incorrect iterator type.Cedric Venet
- fix to please VS: add a return after an assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26stabilize more printing, this doesn't cause a problemChris Lattner
in the example attached to PR2590, but is a problem in general. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55361 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26stablize SubRegsSet printing, part of PR2590Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55360 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26Stabilize 'getDwarfRegNumFull' output to not depend on random memory Chris Lattner
orders, part of PR2590 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55359 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-14Speed up addRegisterDead by adding more fast checks before performing the ↵Owen Anderson
expensive subregister query, and by increasing the size of the subregister hashtable so that there are fewer collisions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54781 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-07TargetRegisterDesc::Name field is the same as the abstract register name. ↵Evan Cheng
There is no need for targets to specify register names in addition to their AsmName's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53207 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01Make the subregister hashtable output more readable by wrapping the lines,Owen Anderson
and mark it const along with the associated changes to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52966 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01Use delete[] instead of free on an array created with new[].Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52960 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01Implement suggestions from Chris:Owen Anderson
- Use a more accurate heuristic for the size of the hashtable. - Use bitwise and instead of modulo since the size is a power of two. - Use new[] instead of malloc(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52951 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01Replace the dynamically computed std::set lookup method for subregisters ↵Owen Anderson
with a hashtable-based version that is computed by tblgen at the time LLVM is compiled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52945 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-30Eliminate TargetRegisterDesc::ImmSubRegs. It's no longer in use.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52892 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-26Fixes the last x86-64 test failure in compat.exp:Dale Johannesen
<16 x float> is 64-byte aligned (for some reason), which gets us into the stack realignment code. The computation changing FP-relative offsets to SP-relative was broken, assiging a spill temp to a location also used for parameter passing. This fixes it by rounding up the stack frame to a multiple of the largest alignment (I concluded it wasn't fixable without doing this, but I'm not very sure.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52750 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06Wrap MVT::ValueType in a struct to get type safetyDuncan Sands
and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-15VisualStudio project files updated. #include <algorithm> added to make ↵Chuck Rose III
VisualStudio happy. Also had to undefine setjmp because of #include <csetjmp> turning setjmp into _setjmp in VisualStudio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49743 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-15Sort sub-registers and super-registers lists according to super-sub register ↵Evan Cheng
relations. e.g. X86::RAX sub-register list is EAX, AX, AL, AH (order of last two are not guaranteed). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49714 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-25Add explicit keywords.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11emit an ID # for each regclass ID. Chris doesn't like to have to count.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48200 91177308-0d34-0410-b5e6-96231b3b80d8
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