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path: root/utils/TableGen/InstrInfoEmitter.cpp
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2010-09-23Add an TargetInstrDesc bit to indicate that a given instruction is a ↵Owen Anderson
conditional move. Not intended functionality change, as nothing uses this yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling
useful after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling
need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling
later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman
MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09How about ULL...Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes
immediates to avoid breaking the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen
When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen
Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19Finally change the instruction looking map to be a densemap fromChris Lattner
record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner
Use CodeGenTarget::getInstNamespace in one place and fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19revert 98912Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19change Target.getInstructionsByEnumValue to return a referenceChris Lattner
to a vector that CGT stores instead of synthesizing it on every call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner
for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09move target-independent opcodes out of TargetInstrInfoChris Lattner
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen
Also, DEBUG_VALUE has side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09Add DEBUG_DECLARE. Not used yet.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08Add DEBUG_VALUE. Not used yet.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman
bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng
set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen
unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24prune the #includes in raw_ostream.h by moving a Chris Lattner
member out of line. ftostr is not particularly speedy, so that method is presumably not perf sensitive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79885 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-291. Introduce a new TargetOperandInfo::getRegClass() helper methodChris Lattner
and convert code to using it, instead of having lots of things poke the isLookupPtrRegClass() method directly. 2. Make PointerLikeRegClass contain a 'kind' int, and store it in the existing regclass field of TargetOperandInfo when the isLookupPtrRegClass() predicate is set. Make getRegClass pass this into TargetRegisterInfo::getPointerRegClass(), allowing targets to have multiple ptr_rc things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29make ptr_rc derive from a new PointerLikeRegClass tblgen class.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77503 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar
- Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman
it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng
instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57722 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman
the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-31Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman
index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman
definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling
instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-03Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman
CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb
LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15Remove isImplicitDef TargetInstrDesc flag.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15Replace all target specific implicit def instructions with a target ↵Evan Cheng
independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng
information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner
both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner
in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10if an instr lacks a pattern, assume it has side effects (unless never has ↵Chris Lattner
s-e is true). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45823 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10start inferring 'no side effects'.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45822 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10Infer mayloadChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45819 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10realize that instructions who match intrinsics that read memory read memory.Chris Lattner
Also, instructions with any nodes that are SDNPMayLoad also read memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45817 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-08add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner
This is currently not set by anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner
Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner
all clients over to using predicates instead of these flags directly. These are now private values which are only to be used to statically initialize the tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner
Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07Move M_* flags down in the file. Move SchedClass up in the Chris Lattner
TargetInstrDescriptor class and shrink to 16-bits, saving a word in TargetInstrDescriptor. Add some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45686 91177308-0d34-0410-b5e6-96231b3b80d8
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