aboutsummaryrefslogtreecommitdiff
path: root/utils/TableGen/EDEmitter.cpp
AgeCommit message (Collapse)Author
2010-11-03Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach
parts. Represent the operation mode as an optional operand instead. rdar://8614429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01factor the operand list (and related fields/operations) out of Chris Lattner
CodeGenInstruction into its own helper class. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Shifter ops are not always free. Do not fold them (especially to formEvan Cheng
complex load / store addressing mode) when they have higher cost and when they have more than one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson
encoding for specifying fractional bits for fixed point conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach
explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach
and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12Fix spelling error.Cameron Esfahani
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08fix bugs in push/pop segment support, rdar://8407242Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01remove dead code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson
instructions besides saturate instructions. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen
the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson
instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach
have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20remove option from tablegen for building static header.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes
notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Implement the major chunk of PR7195: support for 'callw'Chris Lattner
in the integrated assembler. Still some discussion to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Add support for the x86 instructions "pusha" and "popa".Nico Weber
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Next round of tail call changes. Register used in a tailDale Johannesen
call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson
the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Eliminated the classification of control registers into %ecr_Sean Callanan
and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng
coalescer bug that's fixed by 103170. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23Fixes to edis that mark x86 call targets asSean Callanan
memory operands rather than immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14EDis: Don't include inttypes.h. We support compilers which don't provide it. ↵Benjamin Kramer
It was unused anyways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13Fixed a nasty layering violation in the edis sourceSean Callanan
code. It used to #include the enhanced disassembly information for the targets it supported straight out of lib/Target/{X86,ARM,...} but now it uses a new interface provided by MCDisassembler, and (so far) implemented by X86 and ARM. Also removed hacky #define-controlled initialization of targets in edis. If clients only want edis to initialize a limited set of targets, they can set --enable-targets on the configure command line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08Use errs instead of fprintf.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08Added support for ARM disassembly to edis.Sean Callanan
I also added a rule to the ARM target's Makefile to build the ARM-specific instruction information table for the enhanced disassembler. I will add the test harness for all this stuff in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19change Target.getInstructionsByEnumValue to return a referenceChris Lattner
to a vector that CGT stores instead of synthesizing it on every call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14Check in tablegen changes to fix disassembler related failures caused by r98465.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10Updated the enhanced disassembly library's TableGenSean Callanan
backend to not use exceptions at all except in cases of actual error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10Updated the TableGen emitter for the EnhancedSean Callanan
Disassembler to take advantage of the refactored AsmWriterInst.h. Note removed parser code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09Fixed some indentation in the AsmWriterInstSean Callanan
implementation. Also changed the constructor so that it does not require a Record, making it usable by the EDEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-29Quick fix to make the header file for the enhancedSean Callanan
disassembly information have a better comment (and better guard macros). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-29Added a custom TableGen backend to support theSean Callanan
enhanced disassembler, and the necessary makefile rules to build the table for X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94764 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-07 04:22:50 +0000