| Age | Commit message (Expand) | Author |
|---|
| 2006-03-19 | getEnumName() missed v8i8, v4i16, and v2i32 types | Evan Cheng |
| 2006-03-01 | New vector type v2f32. | Evan Cheng |
| 2006-02-20 | Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit | Evan Cheng |
| 2006-01-27 | PHI and INLINEASM are now builtin instructions provided by Target.td | Chris Lattner |
| 2006-01-09 | * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and | Evan Cheng |
| 2005-12-26 | Added field noResults to Instruction. | Evan Cheng |
| 2005-12-23 | * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG | Evan Cheng |
| 2005-12-17 | Support for read / write from explicit registers with FlagVT type. | Evan Cheng |
| 2005-12-08 | * Added an explicit type field to ComplexPattern. | Evan Cheng |
| 2005-12-08 | Added support for ComplexPattern. These are patterns that require C++ pattern | Evan Cheng |
| 2005-12-04 | * Commit the fix (by Chris) for a tblgen type inferencing bug. | Evan Cheng |
| 2005-12-01 | Support multiple ValueTypes per RegisterClass, needed for upcoming vector | Nate Begeman |
| 2005-12-01 | Nuke CodeGenInstruction's ValueType member, it is no longer used. | Nate Begeman |
| 2005-11-29 | Add the new vector types to tablegen | Nate Begeman |
| 2005-11-19 | Initialize this variable on all paths, fixing a crasher in windows. Thanks | Chris Lattner |
| 2005-11-19 | Teach tblgen about instruction operands that have multiple MachineInstr | Chris Lattner |
| 2005-10-28 | Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately | Chris Lattner |
| 2005-10-14 | Do not let getLegalValueTypes return a list with duplicates in it | Chris Lattner |
| 2005-09-14 | force all instruction operands to be named. | Chris Lattner |
| 2005-09-14 | Check that operands have unique names. REJECT instructions with broken operand | Chris Lattner |
| 2005-09-13 | Add a new Record::getValueAsCode method to mirror the other getValueAs* | Chris Lattner |
| 2005-09-08 | Compute the value types that are natively supported by a target. | Chris Lattner |
| 2005-08-26 | spell this right | Chris Lattner |
| 2005-08-26 | spell this variable right | Chris Lattner |
| 2005-08-26 | Expose a new flag to TargetInstrInfo | Chris Lattner |
| 2005-08-19 | Split register class "Methods" into MethodProtos and MethodBodies | Chris Lattner |
| 2005-08-19 | Read the namespace field from register classes | Chris Lattner |
| 2005-08-19 | Fix a problem jeffc noticed | Chris Lattner |
| 2005-08-18 | Figure out how many operands each instruction has, keep track of whether | Chris Lattner |
| 2005-04-22 | Remove trailing whitespace | Misha Brukman |
| 2005-01-22 | Refactor code for numbering instructions into CodeGenTarget. | Chris Lattner |
| 2005-01-02 | Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. | Chris Lattner |
| 2004-10-14 | * Add option to read isLittleEndianEncoding for InstrInfo classes | Misha Brukman |
| 2004-10-03 | Add initial support for variants. This just parses the new format, no | Chris Lattner |
| 2004-09-28 | Add support for the isLoad and isStore flags, needed by the instruction sched... | Nate Begeman |
| 2004-09-28 | Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG | Chris Lattner |
| 2004-08-21 | Alignment is now in bits. | Chris Lattner |
| 2004-08-21 | Make alignment be in bits, just like size is | Chris Lattner |
| 2004-08-21 | Support "Methods" in register classes in CodgeGenRegisterClass | Chris Lattner |
| 2004-08-21 | Start parsing register classes into a more structured form | Chris Lattner |
| 2004-08-21 | Read in declared reg sizes | Chris Lattner |
| 2004-08-16 | Use CodeGenRegister class to make reading in of register information more | Chris Lattner |
| 2004-08-14 | Make the AsmWriter a first-class tblgen object. Allow targets to specify | Chris Lattner |
| 2004-08-11 | Start parsing more information from the Operand information | Chris Lattner |
| 2004-08-11 | Remove special case hacks | Chris Lattner |
| 2004-08-01 | Parse the operand list of the instruction. We currently support register and... | Chris Lattner |
| 2004-08-01 | Initial cut at an asm writer emitter. So far, this only handles emission of | Chris Lattner |
| 2004-08-01 | Add, and start using, the CodeGenInstruction class. This class represents | Chris Lattner |
| 2004-08-01 | Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) | Chris Lattner |
| 2004-08-01 | Finegrainify namespacification | Chris Lattner |
