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2013-07-15Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'Eli Bendersky
Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp
2013-03-17Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen
Not passing vector references around makes it possible to use SmallVector in most places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Merge commit 'a662a9862501fc86904e90054f7c1519101d9126'Derek Schuff
Conflicts: include/llvm/CodeGen/IntrinsicLowering.h include/llvm/MC/MCAssembler.h include/llvm/MC/MCObjectStreamer.h lib/LLVMBuild.txt lib/Linker/LinkArchives.cpp lib/MC/MCAssembler.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCParser/AsmParser.cpp lib/MC/MCPureStreamer.cpp lib/MC/WinCOFFStreamer.cpp lib/Makefile lib/Support/Unix/Memory.inc lib/Support/Unix/Process.inc lib/Support/Unix/Program.inc lib/Target/ARM/ARM.h lib/Target/ARM/ARMFastISel.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/X86/CMakeLists.txt lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86TargetMachine.cpp lib/Target/X86/X86TargetObjectFile.cpp lib/Transforms/InstCombine/InstCombineCalls.cpp test/CodeGen/X86/fast-isel-x86-64.ll tools/llc/llc.cpp tools/lto/LTOModule.cpp utils/TableGen/EDEmitter.cpp
2013-01-11Merge commit '1ad9253c9d34ccbce3e7e4ea5d87c266cbf93410'Derek Schuff
deplib features commented out due to removal upstream; will add back as a localmod Conflicts: include/llvm/ADT/Triple.h include/llvm/MC/MCAssembler.h include/llvm/Target/TargetFrameLowering.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/CodeGen/BranchFolding.cpp lib/LLVMBuild.txt lib/Linker/LinkArchives.cpp lib/MC/MCAssembler.cpp lib/MC/MCELFStreamer.cpp lib/Makefile lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMFrameLowering.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMSubtarget.h lib/Target/ARM/ARMTargetObjectFile.cpp lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsInstrInfo.td lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86Subtarget.h lib/VMCore/Module.cpp test/MC/MachO/ARM/nop-armv4-padding.s tools/Makefile tools/llc/llc.cpp tools/lto/LTOModule.cpp tools/lto/lto.cpp
2012-12-24Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Sort the #include lines for utils/...Chandler Carruth
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06Merge commit 'cfe09ed28d8a65b671e8b7a716a933e98e810e32'Derek Schuff
Conflicts: lib/Target/ARM/ARMFrameLowering.cpp lib/Target/Mips/MipsRegisterInfo.cpp lib/Target/X86/X86ISelLowering.cpp lib/Transforms/IPO/ExtractGV.cpp tools/Makefile tools/gold/gold-plugin.cpp The only interesting conflict was X86ISelLowering.ccp, which meant I had to essentially revert r167104. The problem is that we are using ESP as the stack pointer in X86ISelLowering and RSP as the stack pointer in X86FrameLowering, and that revision made them both consistently use X86RegisterInfo to determine which to use.
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Merge commit 'bc4021f31eaa97ee52655828da3e3de14a39e4a6'Derek Schuff
Conflicts: lib/MC/MCAssembler.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp lib/Target/X86/X86ISelLowering.h
2012-09-19Add in new data types that are used by AMDIL/ANL among others.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Merge commit '8e70b5506ec0d7a6c2740bc89cd1b8f12a78b24f'Derek Schuff
Conflicts: include/llvm/CodeGen/ISDOpcodes.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h include/llvm/Target/TargetOpcodes.h lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp lib/Target/Mips/MipsMCInstLower.cpp utils/TableGen/CodeGenTarget.cpp
2012-09-11Compute a map from register names to registers, rather than scanning the ↵Owen Anderson
list of registers every time we want to look up a register by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem
allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen
Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21Merge up to r162331, git commit bc363931085587bac42a40653962a3e5acd1ffceDerek Schuff
2012-07-09LOCALMODs from hg 0b098ca44de7 against r158408 (hg 90a87d6bfe45)Derek Schuff
(only non-new files; new files in git 4f429c8b) Change-Id: Ia39f818088485bd90e4d048db404f8d6ba5f836b
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27rdar://11542750 - llvm.trap should be marked no return.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach
This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Added MVT::v2f16Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add basic generic CodeGen support for half.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06First chunk of MachineInstr bundle support.Evan Cheng
1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne
This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen
This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Unconstify InitsDavid Greene
Remove const qualifiers from Init references, per Chris' request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Constify InitsDavid Greene
Make references to Inits const everywhere. This is the final step before making them unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher
in multiple buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11[AVX] Make Inits FoldableDavid Greene
Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Add support for alternative register names, useful for instructions whose ↵Owen Anderson
operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen
Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Fix formatting.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson
features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen
Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen
Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen
Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Move TableGen's register bank classes to their own source file.Jakob Stoklund Olesen
I'll be moving some more code there to gather all of the register-specific stuff in one place. Currently it is shared between CodeGenTarget and RegisterInfoEmitter. The plan is that CodeGenRegisters can compute the full register bank structure while RegisterInfoEmitter only will handle the printing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Change how tblgen generates attributes for intrinsics to use a singleJohn McCall
switch. With this newfound organization, teach tblgen how not to give all intrinsics the 'nounwind' attribute. Introduce a new intrinsic, llvm.eh.resume, which does not have this attribute. Documentation and uses to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen
The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Don't allow per-register spill size and alignment.Jakob Stoklund Olesen
These values were not used for anything. Spill size and alignment is a property of the register class, not the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Make the register enum value part of the CodeGenRegister struct.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Flag -> Glue, the ongoing sagaChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
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