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We now match all of 403.gcc (as emitted by clang). :)
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- Used to mark fake instructions which don't correspond to an actual machine
instruction (or are duplicates of a real instruction). This is to be used for
"special cases" in the .td files, which should be ignored by things like the
assembler and disassembler. We still need a good solution to handle pervasive
duplication, like with the Int_ instructions.
- Set the bit on fake "mov 0" style instructions, which allows turning an
assembler matcher warning into a hard error.
- -2 FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78731 91177308-0d34-0410-b5e6-96231b3b80d8
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used to strip hard coded comments out of .td assembly strings.
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related.
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- This drops us to 123 ambiguous instructions (previously ~500) on X86.
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on target specific operands for testing class membership and converting to
MCInst operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78597 91177308-0d34-0410-b5e6-96231b3b80d8
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explicit parser match classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78588 91177308-0d34-0410-b5e6-96231b3b80d8
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structure.
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instruction operands.
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make it easier to see interesting ambiguities.
- Also, check that user doesn't try to redefine the super class. This is a wart
in the current design, in that assembler match classes aren't explicitly
declared somewhere (so there isn't a unique place to declare the super
class). This should probably be fixed.
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- We can now discriminate SUB32ri8 from SUB32ri, for example.
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- We want the ordering operation to be simple, since we run it on every
match. The old ordering is also not a strict weak ordering when there are
ambiguities, which makes MSVC unhappy.
- While we are at it, detect all ambiguities instead of just the adjacent
ones. There are actually 655, for X86.
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-2 FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78523 91177308-0d34-0410-b5e6-96231b3b80d8
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ambiguities.
- Currently there are 483 ambiguities to resolve. :)
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- Track whether we need to insert an explicit 'break'.
- Invert conditional when matching a single prefix to reduce
nesting/bracing/breaking.
- wc -l of X86GenAsmMatcher.inc decreased by 10%. :)
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Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.
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much more efficient way than a sequence of if's. Switch MatchRegisterName
to use it. It would be nice if someone could factor this out to a shared
place in tblgen :)
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- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78461 91177308-0d34-0410-b5e6-96231b3b80d8
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so that terminal states are as simple as possible.
- If we were willing to assume that the order that operands get inserted in the
MCInst is fixed we could actually dispose with this altogether, although it
might be nice to have the flexibility to change it later.
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routine.
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- Still not very sane, but a least its not 60k lines on X86. :)
- In terms of correctness, currently some things are hard wired for X86, and we
still don't properly resolve ambiguities (this is ignoring the instructions
we don't even match due to funny .td stuff or other corner cases).
The high level changes:
1. Represent tokens which are significant for matching explicitly as separate
operands. This uniformly handles not only the instruction mnemonic, but
also 'signficiant' syntax like the '*' in "call * ...".
2. Separate the matching of operands to an instruction from the construction of
the MCInst. In theory this can be done during matching, but since the number
of variations is small I think it makes sense to decompose the problems.
3. Improved a few of the mechanisms to at least successfully flatten / tokenize
the assembly strings for PowerPC and ARM.
4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
moving towards for handling ambiguous instructions. The high-bit is to infer
a partial ordering of the operand classes (and force the user to specify one
if we can't) and use that to resolve ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78378 91177308-0d34-0410-b5e6-96231b3b80d8
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functions.
- Fix variant flattening when the variant embeds an operand reference.
- Ignore instructions which reference an operand multiple times (e.g., "xorb
$dst, $dst"), and operands which have extra flags (e.g., "$dst:subreg32").
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operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77837 91177308-0d34-0410-b5e6-96231b3b80d8
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- This is "experimental" code, I am feeling my way around and working out the
best way to do things (and learning tblgen in the process). Comments welcome,
but keep in mind this stuff will change radically.
- This is enough to match "subb" and friends, but not much else. The next step is to
automatically generate the matchers for individual operands.
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