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2013-04-12Add support for additional vector instructions in the interpreter.Nadav Rotem
patch by Veselov, Yuri <Yuri.Veselov@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Have the StripMetadata pass also strip unsupported named metadata.Jan Voung
Previously it was just instruction attachments. Depends on a driver change to actually work: https://codereview.chromium.org/14072004/ BUG= http://code.google.com/p/nativeclient/issues/detail?id=3348 Review URL: https://codereview.chromium.org/14022009
2013-04-12PNaCl: extend GlobalCleanup to null-out extern_weak function references, and ↵Derek Schuff
extend the ABI checker to verify. Also promote weak symbols to internal ones, which was required because the scons barebones tests define weak versions of memcpy/memset BUG= https://code.google.com/p/nativeclient/issues/detail?id=3339 TEST= llvm-regression (globalcleanup.ll), scons barebones tests Review URL: https://codereview.chromium.org/13989005
2013-04-12PNaCl ABI checker: Disallow ConstantExprs inside functionsMark Seaborn
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3337 TEST=test/NaCl/PNaClABI/*.ll Review URL: https://codereview.chromium.org/13932023
2013-04-12PNaCl ABI checker: Disallow va_arg, varargs functions and varargs callsMark Seaborn
This doesn't disallow the va_start/va_end/va_copy intrinsics yet; these will get disallowed later when we add whitelisting of intrinsics to the PNaCl ABI checker. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3338 TEST=test/NaCl/PNaClABI/*.ll Review URL: https://codereview.chromium.org/13884013
2013-04-12PNaCl ABI checker: Disallow invoke+landingpad instructionsMark Seaborn
The first release of the stable PNaCl ABI won't support zero-cost C++ exception handling. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3377 TEST=toolchain trybots + gcc torture tests + Spec2k + LLVM regression tests Review URL: https://codereview.chromium.org/14044006
2013-04-12ARM: Correct printing of pre-indexed operands.Quentin Colombet
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Simplify (A & ~B) in icmp if A is a power of 2David Majnemer
The transform will execute like so: (A & ~B) == 0 --> (A & B) != 0 (A & ~B) != 0 --> (A & B) == 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12LoopVectorizer: integer division is not a reduction operationArnold Schwaighofer
Don't classify idiv/udiv as a reduction operation. Integer division is lossy. For example : (1 / 2) * 4 != 4/2. Example: int a[] = { 2, 5, 2, 2} int x = 80; for() x /= a[i]; Scalar: x /= 2 // = 40 x /= 5 // = 8 x /= 2 // = 4 x /= 2 // = 2 Vectorized: <80, 1> / <2,5> //= <40,0> <40, 0> / <2,2> //= <20,0> 20*0 = 0 radar://13640654 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179381 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12AArch64: use full triple for ELF testsTim Northover
These tests rely specifically on the names of ELF relocations, let alone any other detail. There's no way they'd work if LLVM was emitting something else by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179376 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12AArch64: remove over-zealous use of CHECK-NEXTTim Northover
It turns out some platforms (e.g. Windows) lay out their llvm-mc slightly differently with extra newlines; there was no real reason for the test lines to be consecutive, so this relaxes the FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179375 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Teach llvm-readobj to print ELF program headersNico Rieck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Remove obsolete object file dumpersNico Rieck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Replace coff-/elf-dump with llvm-readobjNico Rieck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Add extensive relocation tests for llvm-readobjNico Rieck
This test ensures that relocation type names returned by libObject match the raw relocation type value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Fix the test on linux by setting the triple and the align formatNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Add a flag to align all basic blocks in the function.Nadav Rotem
When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Add 179294 back, but don't use bit fields so that it works on big endian hosts.Rafael Espindola
Original message: Print more information about relocations. With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179345 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Aliasing rules for struct-path aware TBAA.Manman Ren
Added PathAliases to check if two struct-path tags can alias. Added command line option -struct-path-tbaa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Use FileCheck instead of grep.Preston Gurd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Optimize icmp involving addition betterDavid Majnemer
Allows LLVM to optimize sequences like the following: %add = add nsw i32 %x, 1 %cmp = icmp sgt i32 %add, %y into: %cmp = icmp sge i32 %x, %y as well as: %add1 = add nsw i32 %x, 20 %add2 = add nsw i32 %y, 57 %cmp = icmp sge i32 %add1, %add2 into: %add = add nsw i32 %y, 37 %cmp = icmp sle i32 %cmp, %x git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Mips specific inline asm memory operand modifier test caseJack Carter
These changes are based on commit responses for r179135. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Revert my last two commits while I debug what is wrong in a big endian host.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179303 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Print more information about relocations.Rafael Espindola
With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Fix for wrong instcombine on vector insert/extractBenjamin Kramer
When trying to collapse sequences of insertelement/extractelement instructions into single shuffle instructions, there is one specific case where the Instruction Combiner wrongly updates the resulting Mask of shuffle indexes. The problem is in function CollectShuffleElments. If we have a sequence of insert/extract element instructions like the one below: %tmp1 = extractelement <4 x float> %LHS, i32 0 %tmp2 = insertelement <4 x float> %RHS, float %tmp1, i32 1 %tmp3 = extractelement <4 x float> %RHS, i32 2 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 3 Where: . %RHS will have a mask of [4,5,6,7] . %LHS will have a mask of [0,1,2,3] The Mask of shuffle indexes is wrongly computed to [4,1,6,7] instead of [4,0,6,7]. When analyzing %tmp2 in order to compute the Mask for the resulting shuffle instruction, the algorithm forgets to update the mask index at position 1 with the index associated to the element extracted from %LHS by instruction %tmp1. Patch by Andrea DiBiagio! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add a CHECK-NOT for a more faithful translation of the original grep | count 2.Eli Bendersky
Thanks to Reid Kleckner for catching this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179289 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add missing colons to check lines.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179277 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11FileCheckize a bunch of tests.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179276 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Optimize vector select from all 0s or all 1sMichael Liao
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add CLAC/STAC instruction encoding/decoding supportMichael Liao
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Enhance bool simplifcation in X86 to handle more casesMichael Liao
This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add MachO-x86-64 tests.Rafael Espindola
The object was already checked in, but was not being tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179256 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Rewrite some of the test/CodeGen/X86 tests to use FileCheck instead of grepEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179241 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10MC: Support COFF image-relative MCSymbolRefsNico Rieck
Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Manually remove successors in if conversion when CopyAndPredicateBlock is usedHal Finkel
In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Mips specific inline asm memory operand modifier test caseJack Carter
These changes are based on commit responses for r179135. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Revert "Update the version of dwarf we say we're emitting to at least 3."Eric Christopher
temporarily while we work on plumbing through some changes to continue supporting gdb on darwin. This reverts commit r179122. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Add object-emission flag for lit tests. This flag is usedJyotsna Verma
to disable following tests for Hexagon that require direct object generation support. DebugInfo/dwarf-public-names.ll DebugInfo/dwarf-version.ll DebugInfo/member-pointers.ll DebugInfo/namespace.ll DebugInfo/two-cus-from-same-file.ll Fixes bug 15616 - http://llvm.org/bugs/show_bug.cgi?id=15616 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Make the SLP store-merger less paranoid about function calls. We check for ↵Nadav Rotem
function calls when we check if it is safe to sink instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: Add pattern for AMDGPUurecipMichel Danzer
21 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10This is for an experimental option -mips-os16. The idea is to compile allReed Kotler
Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Use a scheme closer to that of GNU as when deciding the type of aPeter Collingbourne
symbol with multiple .type declarations. Differential Revision: http://llvm-reviews.chandlerc.com/D607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10PNaCl ABI checker: Disallow the GetElementPtr instructionMark Seaborn
This instruction is removed by ExpandGetElementPtr. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3343 TEST=test/NaCl/PNaClABI/instructions.ll + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/14071005
2013-04-10PNaCl ABI checker: Disallow "section", "thread_local" and "gc" attributesMark Seaborn
* Disallow "section" on functions and global variables. * Disallow "thread_local" on global variables. * Disallow "gc" on functions. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2837 BUG= https://code.google.com/p/nativeclient/issues/detail?id=3126 TEST=test/NaCl/PNaClABI/global-attributes.ll + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/14063007
2013-04-10R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10[test] Use lit's shell test runner on WindowsReid Kleckner
Summary: I did a local comparison between using bash and using lit's runner, and more of the suite passes with lit than passes with bash. Most of the bash failures have to do with /dev/null, which is nonsensical on Windows, but the lit runner handles it. The lit shell runner is also much faster than bash, so I would expect most Windows devs would want it by default. The behavior can be overridden on any OS by setting LIT_USE_INTERNAL_SHELL to 0 or 1 in the environment. Reviewers: chapuni, ddunbar CC: llvm-commits, timurrrr Differential Revision: http://llvm-reviews.chandlerc.com/D559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: dynamical figure out the reg class of MIMGChristian Konig
Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: adjust writemask to only the used componentsChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
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