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2013-05-22PNaCl: Add ReplacePtrsWithInts pass for stripping out pointer typesMark Seaborn
ReplacePtrsWithInts converts IR to a normal form in which functions don't reference any aggregate pointer types and pointer types only appear inside a few instructions. Change BlockAddress::replaceUsesOfWithOnConstant() to handle changing a function's type by replacing a function with a bitcast ConstantExpr of a new function. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3343 TEST=replace-ptrs-with-ints.ll + PNaCl toolchain trybots, torture tests, etc. Review URL: https://codereview.chromium.org/14262011
2013-05-22Merging r182485:Bill Wendling
------------------------------------------------------------------------ r182485 | arnolds | 2013-05-22 09:54:56 -0700 (Wed, 22 May 2013) | 7 lines LoopVectorize: Make Value pointers that could be RAUW'ed a VH The Value pointers we store in the induction variable list can be RAUW'ed by a call to SCEVExpander::expandCodeFor, use a TrackingVH instead. Do the same thing in some other places where we store pointers that could potentially be RAUW'ed. Fixes PR16073. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22Merging r182486:Bill Wendling
------------------------------------------------------------------------ r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned. Take #2 on fixing PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22PNaCl: Fix ExpandCtors to handle an empty list caseMark Seaborn
While writing a test, I noticed that ExpandCtors crashes if given the empty list "[]", because this gets converted into an UndefValue ConstantExpr by the LLVM assembly reader. Fix this by checking the array's size via its type. This replaces the isNullValue() check. Make error handling cleaner by splitting out a separate function. BUG=none TEST=test/Transforms/NaCl/expand-ctors-emptylist.ll Review URL: https://codereview.chromium.org/15659005
2013-05-21Merging r181366:Bill Wendling
------------------------------------------------------------------------ r181366 | enderby | 2013-05-07 14:40:58 -0700 (Tue, 07 May 2013) | 6 lines Fix a bug in the MC asm parser evaluating expressions. It was treating: A = 9 B = 3 * A - 2 * A + 1 as B = 3 * A - (2 * A + 1) rdar://13816516 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182387:Bill Wendling
------------------------------------------------------------------------ r182387 | jholewinski | 2013-05-21 07:37:16 -0700 (Tue, 21 May 2013) | 7 lines Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. The intrinsic calls are dropped, but the annotated value is propagated. Fixes PR 15253 Original patch by Zeng Bin! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182364:Bill Wendling
------------------------------------------------------------------------ r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182344:Bill Wendling
------------------------------------------------------------------------ r182344 | mren | 2013-05-20 17:57:22 -0700 (Mon, 20 May 2013) | 7 lines Dwarf: use a single line table to generate assembly when .loc is used. This is to fix PR15408 where an undefined symbol Lline_table_start1 is used. Since we do not generate the debug_line section when .loc is used, Lline_table_start1 is not emitted and we can't refer to it when calculating at_stmt_list for a compile unit. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20Create type IDs based on reference counts.Karl Schimpf
Create type IDs based on number of references, rather than first reached. This is done so that fewer bits are used to encode types that are commonly used. Note that this cuts the size of the generate bitcode file by about 1.5%, with no effect on the reader, since it only changes the order type ID's are created. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3405 R=jvoung@chromium.org Review URL: https://codereview.chromium.org/14495008
2013-05-20Fix stderr redirection in test to work on all platformsEli Bendersky
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/15470008
2013-05-20PNaCl: Fix FlattenGlobals to correctly handle implicitly-aligned variablesMark Seaborn
If a global variable has no "align" attribute, it must be aligned based on its type. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3437 TEST=flatten-globals.ll Review URL: https://codereview.chromium.org/15359006
2013-05-17Merging r182113:Bill Wendling
------------------------------------------------------------------------ r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines R600: Fix encoding for R600 family GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Re-allow an x86-32 fast-isel optimization for NaCl / use shorter insts.Jan Voung
There was an old fix for r+r based memory references on x86-64 that checked for isTargetNaCl() instead of isTargetNaCl64(). This disabled some r+r for 32-bit. However, fast isel only sets up r+r with geps, and we don't have geps in the stable ABI. We could potentially add some similar pattern matching in the future... The problem we *do* see with the current bitcode, is that this change also made it preferred to use an index register instead of a base register. This made the memory references on x86-32 look like: cmpl ..., (,%eax,1) instead of cmpl ..., (%eax) So we had longer instructions. Total zipped nexe sizes: 5.73MB (old) vs 5.59 MB (new) (2.5%) Total not zipped: 17.28MB vs 16.28 MB (6%) runtime diffs (min of 5 runs) * eon 4.94 (old) vs 4.72 (new) (~4%) * mesa 21.64 vs 21.08 * mcf 5.76 vs 5.60 * vortex 4.21 vs 4.05 * perlbmk 27.62 vs 26.55 (the rest were under 2% better) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3359 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/15047013
2013-05-17Merging r181678:Bill Wendling
------------------------------------------------------------------------ r181678 | rafael | 2013-05-12 17:18:24 -0700 (Sun, 12 May 2013) | 1 line XFAIL this test for mingw too. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r181600:Bill Wendling
------------------------------------------------------------------------ r181600 | aaronballman | 2013-05-10 07:42:16 -0700 (Fri, 10 May 2013) | 1 line XFAILing this test on Win32 to unbreak the build bots. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Cherry-pick r181922: Fix miscompile due to StackColoring incorrectly merging ↵Mark Seaborn
stack slots (PR15707) IR optimisation passes can result in a basic block that contains: llvm.lifetime.start(%buf) ... llvm.lifetime.end(%buf) ... llvm.lifetime.start(%buf) Before this change, calculateLiveIntervals() was ignoring the second lifetime.start() and was regarding %buf as being dead from the lifetime.end() through to the end of the basic block. This can cause StackColoring to incorrectly merge %buf with another stack slot. Fix by removing the incorrect Starts[pos].isValid() and Finishes[pos].isValid() checks. Just doing: Starts[pos] = Indexes->getMBBStartIdx(MBB); Finishes[pos] = Indexes->getMBBEndIdx(MBB); unconditionally would be enough to fix the bug, but it causes some test failures due to stack slots not being merged when they were before. So, in order to keep the existing tests passing, treat LiveIn and LiveOut separately rather than approximating the live ranges by merging LiveIn and LiveOut. This fixes PR15707. Patch by Mark Seaborn. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3374 Review URL: https://codereview.chromium.org/15302009
2013-05-16Temporarily remove test that fails on MacEli Bendersky
BUG=None Review URL: https://codereview.chromium.org/15100013
2013-05-16Merging r181540:Bill Wendling
------------------------------------------------------------------------ r181540 | void | 2013-05-09 13:10:38 -0700 (Thu, 09 May 2013) | 11 lines Generate a compact unwind encoding in the face of a stack alignment push. We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181580:Bill Wendling
------------------------------------------------------------------------ r181580 | tstellar | 2013-05-09 19:09:45 -0700 (Thu, 09 May 2013) | 10 lines R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181954 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181579:Bill Wendling
------------------------------------------------------------------------ r181579 | tstellar | 2013-05-09 19:09:39 -0700 (Thu, 09 May 2013) | 8 lines R600: Expand SUB for v2i32/v4i32 Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181578:Bill Wendling
------------------------------------------------------------------------ r181578 | tstellar | 2013-05-09 19:09:34 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand MUL for v4i32/v2i32 Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181577:Bill Wendling
------------------------------------------------------------------------ r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand SRA for v4i32/v2i32 v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181951 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181576:Bill Wendling
------------------------------------------------------------------------ r181576 | tstellar | 2013-05-09 19:09:24 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand vselect for v4i32 and v2i32 v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Merging r181842:Bill Wendling
------------------------------------------------------------------------ r181842 | arnolds | 2013-05-14 15:33:24 -0700 (Tue, 14 May 2013) | 14 lines ARM ISel: Don't create illegal types during LowerMUL The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Merging r181524:Bill Wendling
------------------------------------------------------------------------ r181524 | rafael | 2013-05-09 10:22:59 -0700 (Thu, 09 May 2013) | 4 lines Don't replace an alias in llvm.used with its target. When we replace an internal alias with its target, be careful not to replace the entry in llvm.used (and llvm.compiler_used). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181909 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Update tests to use FileCheck instead of grep (which is deprecated in the ↵Eli Bendersky
LLVM regression suite) BUG=None R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/15042009
2013-05-14Merging r181800:Bill Wendling
------------------------------------------------------------------------ r181800 | wschmidt | 2013-05-14 09:08:32 -0700 (Tue, 14 May 2013) | 15 lines PPC32: Fix stack collision between FP and CR save areas. The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Merging r181586:Bill Wendling
------------------------------------------------------------------------ r181586 | d0k | 2013-05-10 02:16:52 -0700 (Fri, 10 May 2013) | 3 lines InstCombine: Verify the type before transforming uitofp into select. PR15952. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Adding a pass - RewritePNaClLibraryCalls, that replaces known library calls ↵Eli Bendersky
with stable bitcode intrinsics. Starting with setjmp and longjmp. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=jvoung@chromium.org, mseaborn@chromium.org Review URL: https://codereview.chromium.org/14617017
2013-05-14Update PNaCl intrinsic whitelist test for moving {frame,return}address to ↵Jan Voung
blacklist. Forgot to do this in last CL: https://codereview.chromium.org/14657017/ BUG=https://code.google.com/p/nativeclient/issues/detail?id=3378 R=dschuff@chromium.org Review URL: https://codereview.chromium.org/14774009
2013-05-10PNaCl ABI: Promote illegal integer typesDerek Schuff
This pass (mostly) legalizes integer types by promoting them. It has some limitations (e.g. it can't change function types) but it is more than sufficient for what clang and SROA generate. A more significant limitation of promotion is that packed bitfields of size > 64 bits are still not handled. There are none in our tests (other than callingconv_case_by_case which doesn't require a stable pexe) but we will want to either handle them by correctly expanding them, or find a better way to error out. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3360 R=eliben@chromium.org, jvoung@chromium.org Review URL: https://codereview.chromium.org/14569012
2013-05-10LLVM: Add ELF Note section to NaCl object files identifying them as such to goldDerek Schuff
This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009
2013-05-10Merging r181397:Bill Wendling
------------------------------------------------------------------------ r181397 | nicholas | 2013-05-08 02:00:10 -0700 (Wed, 08 May 2013) | 3 lines Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInst by switching to a ValueMap. Patch by Andrea DiBiagio! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-09Support @llvm.nacl.{set|long}jmp intrinsics by translating them to library callsEli Bendersky
This is similar to the way @llvm.{set|long}jmp are handled. The previously defined nacl-specific intrinsics are no longer used and are overridden. For the library call, call setjmp/longjmp without a preceding underscore as these symbols exist in our runtime support code (pnacl/support/setjmp_XXX.S) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/14715018
2013-05-09Add a llvm lit test for NaCl ARM/X86 support for bswap i16, i32, i64.Jan Voung
Slowly trying to promote "dev" intrinsics that are being tested to be accepted. Luckily, bswap is supported without compiler_rt for ARM and x86 at least. Test at default level and -O0. Also tested by gcc/testsuite/gcc.dg/builtin-bswap-[1,2,3,4,5].c, and a couple of other gcc tests. We may want to blacklist odd argument sizes like i8, and i1, which the x86 backend won't handle. The i16 case is also interesting, however, it's easy to do if you have an i32 bswap. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3378 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14971004
2013-05-09PNaCl: Add NoAlias attributes in ExpandByVal and ExpandVarArgs passesMark Seaborn
This could help prevent these expansion passes from inhibiting optimisations than run after the expansion. e.g. It gives the optimiser more freedom to move around reads from the varargs buffer because they will not alias writes to other locations. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3400 TEST=PNaCl toolchain trybots + GCC torture tests + LLVM test suite + Spec2k Review URL: https://codereview.chromium.org/14060026
2013-05-09Merging r181423:Bill Wendling
------------------------------------------------------------------------ r181423 | hfinkel | 2013-05-08 05:16:14 -0700 (Wed, 08 May 2013) | 5 lines PPCInstrInfo::optimizeCompareInstr should not optimize FP compares The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Merging r181286:Bill Wendling
------------------------------------------------------------------------ r181286 | arnolds | 2013-05-06 21:37:05 -0700 (Mon, 06 May 2013) | 7 lines LoopVectorize: getConsecutiveVector must respect signed arithmetic We were passing an i32 to ConstantInt::get where an i64 was needed and we must also pass the sign if we pass negatives numbers. The start index passed to getConsecutiveVector must also be signed. Should fix PR15882. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Insert denominator zero checks for NaClDavid Sehr
This IR pass for ARM inserts a comparison and a branch to trap if the denominator of a DIV or REM instruction is zero. This makes ARM fault identically to x86 in this case. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2833 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14607004
2013-05-07Start a whitelist of intrinsics for the PNaCl ABI checker.Jan Voung
This list is currently too small to support our tests (scons, gcc, llvm). To prevent the tests from breaking, there is a -pnaclabi-allow-intrinsics flag which defaults to true. To turn on the checking for real, set -pnaclabi-allow-intrinsics=0. We will avoid actually using the -pnaclabi-allow-intrinsics flags in tests, and try to just stick with the -pnacl-disable-abi-check flag. Remove this flag soon. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3378 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14670017
2013-05-06DebugInfo: Support imported modules in lexical blocksDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06InstCombine: (X ^ signbit) + C -> X + (signbit ^ C)David Majnemer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Reduce attributes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Split Alignment out of the Section Characteristics.Rafael Espindola
The alignment is just a byte in the middle of Characteristics, not an independent flag. Making it an independent field in the yaml representation makes it more yamlio friendly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Test results verified using FileCheck rather than grep | countJean-Luc Duprat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181234 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Rotate multi-exit loops even if the latch was simplified.Andrew Trick
Test case by Michele Scandale! Fixes PR10293: Load not hoisted out of loop with multiple exits. There are few regressions with this patch, now tracked by rdar:13817079, and a roughly equal number of improvements. The regressions are almost certainly back luck because LoopRotate has very little idea of whether rotation is profitable. Doing better requires a more comprehensive solution. This checkin is a quick fix that lacks generality (PR10293 has a counter-example). But it trivially fixes the case in PR10293 without interfering with other cases, and it does satify the criteria that LoopRotate is a loop canonicalization pass that should avoid heuristics and special cases. I can think of two approaches that would probably be better in the long run. Ultimately they may both make sense. (1) LoopRotate should check that the current header would make a good loop guard, and that the loop does not already has a sufficient guard. The artifical SimplifiedLoopLatch check would be unnecessary, and the design would be more general and canonical. Two difficulties: - We need a strong guarantee that we won't endlessly rotate, so the analysis would need to be precise in order to avoid the SimplifiedLoopLatch precondition. - Analysis like this are usually based on SCEV, which we don't want to rely on. (2) Rotate on-demand in late loop passes. This could even be done by shoving the loop back on the queue after the optimization that needs it. This could work well when we find LICM opportunities in multi-branch loops. This requires some work, and it doesn't really solve the problem of SCEV wanting a loop guard before the analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Emit config values in register / value pairsTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Stop emitting the instruction type byte before each instructionTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Emit ISA for CALL_FS_* instructionsTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06[SystemZ] Update non-pic DWARF encodingsUlrich Weigand
As pointed out by Rafael Espindola, we should match the DWARF encodings produced by GCC in both pic and non-pic modes. This was not the case for the non-pic case. This patch changes all DWARF encodings to DW_EH_PE_absptr for the non-pic case, just like GCC does. The test case is updated to check for both variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181222 91177308-0d34-0410-b5e6-96231b3b80d8
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