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2012-04-08Teach LLVM about a PIE option which, when enabled on top of PIC, makesChandler Carruth
optimizations which are valid for position independent code being linked into a single executable, but not for such code being linked into a shared library. I discussed the design of this with Eric Christopher, and the decision was to support an optional bit rather than a completely separate relocation model. Fundamentally, this is still PIC relocation, its just that certain optimizations are only valid under a PIC relocation model when the resulting code won't be in a shared library. The simplest path to here is to expose a single bit option in the TargetOptions. If folks have different/better designs, I'm all ears. =] I've included the first optimization based upon this: changing TLS models to the *Exec models when PIE is enabled. This is the LLVM component of PR12380 and is all of the hard work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-08AVX2: Build splat vectors by broadcasting a scalar from the constant pool.Nadav Rotem
Previously we used three instructions to broadcast an immediate value into a vector register. On Sandybridge we continue to load the broadcasted value from the constant pool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-071. Remove the part of r153848 which optimizes shuffle-of-shuffle into a newNadav Rotem
shuffle node because it could introduce new shuffle nodes that were not supported efficiently by the target. 2. Add a more restrictive shuffle-of-shuffle optimization for cases where the second shuffle reverses the transformation of the first shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154266 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-07Convert floating point division by a constant into multiplication by theDuncan Sands
reciprocal if converting to the reciprocal is exact. Do it even if inexact if -ffast-math. This substantially speeds up ac.f90 from the polyhedron benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-07Make the test for r154235 more platform-independent with a shorterSean Hunt
string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-07Output UTF-8-encoded characters as identifier characters into assemblySean Hunt
by default. This is a behaviour configurable in the MCAsmInfo. I've decided to turn it on by default in (possibly optimistic) hopes that most assemblers are reasonably sane. If this proves a problem, switching to default seems reasonable. I'm not sure if this is the opportune place to test, but it seemed good to make sure it was tested somewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06Test case for PR12413Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06Allow 256-bit shuffles to be split if a 128-bit lane contains elements from ↵Craig Topper
a single source. This is a rewrite of the 256-bit shuffle splitting code based on similar code from legalize types. Fixes PR12413. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05Don't break the IV update in TLI::SimplifySetCC().Jakob Stoklund Olesen
LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154119 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03Add an additional testcase which checks ops with multiple users.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Allocate virtual registers in ascending order.Jakob Stoklund Olesen
This is just the fallback tie-breaker ordering, the main allocation order is still descending size. Patch by Shamil Kurmangaleev! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem
shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01This commit contains a few changes that had to go in together.Nadav Rotem
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Add a triple to the test.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola
This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Testcase for r153710.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29The shuffle scheduler is only available in asserts build - make misched-new.llLang Hames
testcase require asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in ↵Lang Hames
64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones
This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Reverted to revision 153616 to unblock buildJoel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones
This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Add a test for the previous commit. Also, remove two tests that wereEric Christopher
testing a) the wrong behavior or b) something that I'm already testing in the new test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Post-ra LICM should take care not to hoist an instruction that would clobber aEvan Cheng
register that's read by the preheader terminator. rdar://11095580 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153492 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky
* Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Remove -enable-lsr-nested in time for 3.1.Andrew Trick
Tests cases have been removed but attached to open PR12330. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: tag a few XFAILs that I plan to fixAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu toChad Rosier
vextractf128 with 128-bit mem dest. Combines vextractf128 $0, %ymm0, %xmm0 vmovaps %xmm0, (%rdi) to vextractf128 $0, %ymm0, (%rdi) rdar://11082570 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Move the vextractf128 patterns closer to the vextractf128 def. RemoveChad Rosier
whitespace from test case. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Fix test.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.Chad Rosier
This results in things such as vmovups 16(%rdi), %xmm0 vinsertf128 $1, %xmm0, %ymm0, %ymm0 to be combined to vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 rdar://11076953 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling
i128). In that case, we may not be able to print out the MCExpr as an expression. For instance, we could have an MCExpr like this: 0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64) The MCExpr printer handles sizes up to 64-bits, but this expression would require 128-bits. In this situation, try to evaluate the constant expression and emit that as the value into 64-bit chunks. <rdar://problem/11070338> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd
X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem
add the new node into the work list because there is a potential for further optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152784 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[avx] Add patterns for VINSERTF128rm.Chad Rosier
This results in things such as vmovaps -96(%rbx), %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 to be combined to vinsertf128 $1, -96(%rbx), %ymm0, %ymm0 rdar://10643481 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Fix a regression from r147481.Chad Rosier
Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Remove a test case that no longer makes sense.Jakob Stoklund Olesen
This was testing the handling of sub-register coalescing followed by remat. The original problem was caused by the extra <imp-def> operands added by sub-register coalescing. Those <imp-def> operands are not added any longer, and the test case passes even when the original patch is reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Do trivial CSE of dead BBs during codegen preparation.Bill Wendling
Some BBs can become dead after codegen preparation. If we delete them here, it could help enable tail-call optimizations later on. <rdar://problem/10256573> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02Prevent obscure and incorrect tail-call optimization.Chad Rosier
In this instance we are generating the tail-call during legalizeDAG. The 2nd floor call can't be a tail call because it clobbers %xmm1, which is defined by the first floor call. The first floor call can't be a tail-call because it's not in the tail position. The only reasonable way I could think to fix this in a target-independent manner was to check for glue logic on the copy reg. rdar://10930395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Trivial change to make the test use Use –mcpu=generic,Preston Gurd
so that the test will not fail when run on an Intel Atom processor, due to the Atom scheduler producing an instruction sequence that is different from that which is normally expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Revert r151816 as Jim has the appropriate fix.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix testcases from r151807.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Add missing triple for tests.Jim Grosbach
Make darwin bots happier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ↵James Molloy
though they could have sideeffects. Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Don't redundantly copy implicit operands when rematerializing.Lang Hames
While we're at it - don't copy vreg implicit operands while rematerializing. This fixes PR12138. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" ↵Benjamin Kramer
optimization, making the lives of later passes easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28LegalizeIntegerTypes: Reenable the large shift with small amount optimization.Benjamin Kramer
To avoid problems with zero shifts when getting the bits that move between words we use a trick: first shift the by amount-1, then do another shift by one. When amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32. Also fix a latent bug that emitted the low and high words in the wrong order when shifting right. Fixes PR12113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151637 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Fix a bug in the code that builds SDNodes from vector GEPs.Nadav Rotem
When the GEP index is a vector of pointers, the code that calculated the size of the element started from the vector type, and not the contained pointer type. As a result, instead of looking at the data element pointed by the vector, this code used the size of the vector. This works for 32bit members (on 32bit systems), but not for other types. Added code to peel the vector type and added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27test commit.Preston Gurd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 ↵NAKAMURA Takumi
lowering for i386-*-win32 targets. Patch by Joe Groff. [Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems: Clang raised a warning, and X86 LowerOperation would assert out for fptoui f64 to i32 because it improperly lowered to an illegal BUILD_PAIR. Here's a patch that addresses these issues. Let me know if any other changes are necessary. Thanks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Add WIN_FTOL_* psudo-instructions to model the unique calling conventionMichael J. Spencer
used by the Win32 _ftol2 runtime function. Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151382 91177308-0d34-0410-b5e6-96231b3b80d8
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