emscripten-fastcomp - LLVM with the emscripten fastcomp javascript backend

Age	Commit message (Collapse)	Author
2013-03-30	[mips] Fix DSP instructions to have explicit accumulator register operands.	Akira Hatanaka
	Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30	[mips] Move the code which does dag-combine for multiply-add/sub nodes to	Akira Hatanaka
	derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30	Remove unnecessary checking of register operands.	Akira Hatanaka
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09	Fix test cases.	Akira Hatanaka
	Generate code for Mips32r1 unless a Mips32r2 feature is tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18	Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka	Bruno Cardoso Lopes
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123760 91177308-0d34-0410-b5e6-96231b3b80d8