aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/Hexagon
AgeCommit message (Collapse)Author
2013-10-11Cherry-pick LLVM 187787 to prevent tail calls on x86-32 when not appropriate.Jan Voung
See: http://llvm.org/viewvc/llvm-project?view=revision&revision=187787 The newer version of newlib tickles this x86-32 bug when building the exception handling tests, which don't strip the "tail" attribute. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702 Waiting on trybots, but it seems to have fixed the minimal reproducer I have: http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875 R=jfb@chromium.org Review URL: https://codereview.chromium.org/26538008
2013-05-02Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30TBAA: remove !tbaa from testing cases if not used.Manman Ren
This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Hexagon: Remove assembler mapped instruction definitions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma
for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma
Remove noV4T gp-relative instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma
word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Hexagon: Removed asserts regarding alignment and offset.Jyotsna Verma
We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Hexagon: Add patterns for zero extended loads from i1->i64.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07Hexagon: Add support to lower block address.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05reverting patch 176508.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Add support for lowering block address.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Hexagon: Add constant extender support framework.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma
Add HexagonMCInst class which adds various Hexagon VLIW annotations. In addition, this class also includes some APIs related to the constant extenders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma
instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek
- variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add testcase for post-increment store instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma
for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01Hexagon: Test case to confirm generation of indexed loads with zero offset.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Add indexed load/store instructions for offset validation check.Jyotsna Verma
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07In hexagon convertToHardwareLoop, don't deref end() iteratorMatthew Curtis
In particular, check if MachineBasicBlock::iterator is end() before using it to call getDebugLoc(); See also this thread on llvm-commits: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Use multiclass to define store instructions with base+immediate offsetJyotsna Verma
addressing mode and immediate stored value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the ↵NAKAMURA Takumi
failure on i686 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167988 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Added multiclass for post-increment load instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access thePranav Bhandarkar
subreg_hireg of register pair Rp. * lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New DenseMap similar to PeepholeMap that additionally records subreg info too. (runOnMachineFunction): Record information in PeepholeDoubleRegsMap and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to the instruction Rx = COPY Rp1:logreg_subreg. * test/CodeGen/Hexagon/remove_lsr.ll: New test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163214 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Porting Hexagon MI Scheduler to the new API.Sergei Larin
Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen
These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen
Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13[Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer
This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Add test triples to fix win32 failures. Revert workaround from r161292.Bob Wilson
I don't have a win32 system to test, so hopefully I got them all fixed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Refactor and check "onlyReadsMemory" before optimizing builtins.Bob Wilson
This patch is mostly just refactoring a bunch of copy-and-pasted code, but it also adds a check that the call instructions are readnone or readonly. That check was already present for sin, cos, sqrt, log2, and exp2 calls, but it was missing for the rest of the builtins being handled in this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Enable all Hexagon tests.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Revert 156634 upon request until code improvement changes are made.Brendon Cahoon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12Support for Hexagon feature, New Value Jump.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Hexagon constant extender support.Brendon Cahoon
Patch by Jyotsna Verma. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Hexagon V5 FP Support.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Support for target dependent Hexagon VLIW packetizer.Sirish Pande
This patch creates and optimizes packets as per Hexagon ISA rules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-27 23:04:28 +0000