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2010-10-11Found a bug turning this on by default. Disable again for now.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11Remove now non-existent option.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09Correct some load / store instruction itinerary mistakes:Evan Cheng
1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09Simplify test and move into a generic "crash" ll file.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09Check to make sure that the iterator isn't at the beginning of the basic blockBill Wendling
before decrementing. <rdar://problem/8529919> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08Change register allocation order for ARM VFP and NEON registers to put theBob Wilson
callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng
allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30Try again to disable critical edge splitting in CodeGenPrepare.Jakob Stoklund Olesen
The bug that broke i386 linux has been fixed in r115191. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()Jason W Kim
Small test for sanity check of resulting ARM .s file. Tested against -r115129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115133 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.Bob Wilson
LDM/STM instructions can run one cycle faster on some ARM processors if the memory address is 64-bit aligned. Radar 8489376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29do not compare actual branch labels; this may fix ↵Gabor Greif
llvm-gcc-x86_64-darwin10-cross-mingw32 buildbot too git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29improve heuristics to find the 'and' corresponding to 'tst' to also catch ↵Gabor Greif
opportunities on thumb2 added some doxygen on the way git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Add a subtarget hook for reporting the misprediction penalty. Use this to ↵Owen Anderson
provide more precise cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability. Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28User proper libcall names & condcodes while compiling for ARM EABI.Anton Korobeynikov
Patch by Evzen Muller! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Part one of switching to using a more sane heuristic for determining ↵Owen Anderson
if-conversion profitability. Rather than having arbitrary cutoffs, actually try to cost model the conversion. For now, the constants are tuned to more or less match our existing behavior, but these will be changed to reflect realistic values as this work proceeds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Add a command line option "-arm-strict-align" to disallow unaligned memoryBob Wilson
accesses for ARM targets that would otherwise allow it. Radar 8465431. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27Revert "Disable codegen prepare critical edge splitting. Machine instruction ↵Jakob Stoklund Olesen
passes now" This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost. It seems there is a downstream bug that is exposed by -cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back in. Note that the changes to tailcallfp2.ll are not reverted. They were good are required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27Explicitly disable CGP critical edge splitting for this test so it won't breakJakob Stoklund Olesen
by reenabling it temporarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27Don't depend on basic block numbering.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24Enable code placement optimization pass for ARM.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23Set alignment operand for NEON VST instructions.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23Set alignment operand for NEON VLD instructions.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23Disable codegen prepare critical edge splitting. Machine instruction passes nowEvan Cheng
break critical edges on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21OptimizeCompareInstr should avoid iterating pass the beginning of the MBB ↵Evan Cheng
when the 'and' instruction is after the comparison. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach
between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64Bob Wilson
value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach
and shift instructions on ARM. Update the tests to match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Update tests to handle MC-inst instruction printing of shift operations. TheJim Grosbach
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17FileCheck-izeJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Move thumb2 tests to the thumb2 directoryJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17tweak test to check instructions rather than relying on the comment stringJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17tweak test to check instructions rather than relying on the comment stringJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17tweak test to check instructions rather than relying on the comment stringJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Reapply Gabor's 113839, 113840, and 113876 with a fix for a problemBob Wilson
encountered while building llvm-gcc for arm. This is probably the same issue that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, not a plain MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15the darwin9-powerpc buildbot keeps consistently crashing,Gabor Greif
backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14forgot the testcase change for r113839Gabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14test for and-tst peephole optimizationGabor Greif
documents the status-quo with its opportunities git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13Re-apply r113679, which was reverted in r113720, which added a paid of new ↵Owen Anderson
instcombine transforms to expose greater opportunities for store narrowing in codegen. This patch fixes a potential infinite loop in instcombine caused by one of the introduced transforms being overly aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113763 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-12Revert 113679, it was causing an infinite loop in a testcase that I've sentEric Christopher
on to Owen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Fix test so it passes on non-Darwin hosts.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Fix merging base-updates for VLDM/VSTM: Before I switched these instructionsBob Wilson
to use AddrMode4, there was a count of the registers stored in one of the operands. I changed that to just count the operands but forgot to adjust for the size of D registers. This was noticed by Evan as a performance problem but it is a potential correctness bug as well, since it is possible that this could merge a base update with a non-matching immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng
take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08Remove ssp from this test.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113392 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03Replace NEON vabdl, vaba, and vabal intrinsics with combinations of theBob Wilson
vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Fix an unnecessary XFAILSandeep Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Now that register allocation properly considers reserved regs, simplify theJim Grosbach
ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson
after regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,Bob Wilson
add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01temporarily revert r112664, it is causing a decoding conflict, and Chris Lattner
the testcases should be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
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