aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/ARM
AgeCommit message (Collapse)Author
2013-03-22Reorder the DIFile field in DILexicalBlock to become a prefix common with ↵David Blaikie
other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Move the DIFile in DISubprogram to the beginning to be a common prefix along ↵David Blaikie
with other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Fix Darwin NEON FP and increase coverageRenato Golin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Remove unused field in DISubprogramDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177661 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin
NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Debug info: refactor the first field of DICompileUnit to be a raw ↵David Blaikie
file/directory pair This removes the DICompileUnit special case from DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20When computing the demanded bits of Load SDNodes, make sure that we are ↵Nadav Rotem
looking at the loaded-value operand and not the ptr result (in case of pre-inc loads). rdar://13348420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Debug Info: Swap the 2nd and 3rd parameters to DICompileUnit to match the ↵David Blaikie
common DIScope prefix git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177595 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Remove unused field in DICompileUnitDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177590 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to ↵David Blaikie
a raw directory/file pair This makes DIType's first non-tag parameter the same as DIFile's, allowing them to both share the common implementation of getFilename/getDirectory in DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Move the DIFile operand to DITypes from the 4th operand to the 2nd.David Blaikie
This is another step along the way to making all DIScopes have a common prefix which can be added to in a general manner to support using directives (DW_TAG_imported_module). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Improve long vector sext/zext lowering on ARMRenato Golin
The ARM backend currently has poor codegen for long sext/zext operations, such as v8i8 -> v8i32. This patch addresses this by performing a custom expansion in ARMISelLowering. It also adds/changes the cost of such lowering in ARMTTI. This partially addresses PR14867. Patch by Pete Couperus git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177380 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Extend global merge pass to optionally consider global constant variables.Quentin Colombet
Also add some checks to not merge globals used within landing pad instructions or marked as "used". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Remove unnecessary leading comment characters in lit-only fileDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Include '.test' suffix in target specific lit configs that need itDavid Blaikie
Apparently my final cleanup to use a relevant suffix for these tests before committing r176831 caused them to stop running since lit wasn't configured to run tests with that suffix in those directories (why don't we just have a global suffix list?). So, add the suffix to the relevant directories & fix the test that has bitrotted over the last week due to my debug info schema changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17Split out filename & directory from DIFile to start generalizing over DIScopesDavid Blaikie
This is the first step to making all DIScopes have a common metadata prefix (so that things (using directives, for example) that can appear in any scope can be added to that common prefix). DIFile is itself a DIScope so the common prefix of all DIScopes cannot be a DIFile - instead it's the raw filename/directory name pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15ARM cost model: Fix costs for some vector selectsArnold Schwaighofer
I was too pessimistic in r177105. Vector selects that fit into a legal register type lower just fine. I was mislead by the code fragment that I was using. The stores/loads that I saw in those cases came from lowering the conditional off an address. Changing the code fragment to: %T0_3 = type <8 x i18> %T1_3 = type <8 x i1> define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2, %T1_3* %blend, %T0_3* %storeaddr) { %v0 = load %T0_3* %loadaddr %v1 = load %T0_3* %loadaddr2 ==> FROM: ;%c = load %T1_3* %blend ==> TO: %c = icmp slt %T0_3 %v0, %v1 ==> USE: %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1 store %T0_3 %r, %T0_3* %storeaddr ret void } revealed this mistake. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Adding an A15 specific optimization pass for interactions between S/D/Q ↵Silviu Baranga
registers. The pass handles all the required transformations pre-regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15ARM: Fix an old refacto.Benjamin Kramer
Fixes PR15520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14ARM cost model: Increase cost of some vector selects we do terrible onArnold Schwaighofer
By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Remove the unused 4th operand for DIFile debug info metadataDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13ARM cost model: Add test case to make sure we would notice a change in CodeGenArnold Schwaighofer
In r176898 I updated the cost model to reflect the fact that sext/zext/cast on v8i32 <-> v8i8 and v16i32 <-> v16i8 are expensive. This test case is so that we make sure to update the cost model once we fix CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Refactor filename/directory in DICompileUnit into a DIFileDavid Blaikie
This is the next step towards making the metadata for DIScopes have a common prefix rather than having to delegate based on their tag type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Remove unused "isMain" field from DICompileUnitDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176910 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Update debug info test cases with empty SplitDebugFilename field.David Blaikie
This could be 'null' or the empty string, DIDescriptor::getStringField coalesces the two cases anyway so it's just a matter of legible/efficient representation. The change in behavior of the DICompileUnit::get* functions could be subsumed by the full verification check - but ideally that should just be an assertion if we could front-load the actual debug info metadata failure paths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176907 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Revert the test moves from 176733. Use "REQUIRES: asserts" instead.Jan Wen Voung
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Upgrading debug info test cases to be (more) compatible with the current ↵David Blaikie
debug info format. These cases were found by further work to remove support for debug info versioning. Common cleanups (other than changing the version info in the tag field) included adding the last parameter to compile_units (recently added for fission support) and other cases of trailing fields in lexical blocks, compile units, and subprograms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Merge commit '279b9184c2ff4fea93b198a3519b8cb3a1d8d195'Eli Bendersky
Conflicts: include/llvm/CodeGen/LexicalScopes.h include/llvm/MC/MCAsmInfo.h lib/Linker/LinkArchives.cpp lib/Linker/LinkItems.cpp lib/MC/MCAsmInfo.cpp lib/MC/MCDwarf.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/Mips/MipsTargetObjectFile.cpp lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86TargetMachine.cpp lib/Transforms/CMakeLists.txt lib/Transforms/LLVMBuild.txt lib/Transforms/Makefile test/MC/ARM/arm_instructions.s test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
2013-03-11Remove duplicate test contents.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Remove date from test case file name. The PR number provides a unique ID ↵Lang Hames
already. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09Don't glue users to extract_subreg when selecting the llvm.arm.ldrexdLang Hames
intrinsic - it can cause impossible-to-schedule subgraphs to be introduced. PR15053. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09Test case hygiene.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung
Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Revert r176154 in favor of a better approach.Bill Wendling
Code generation makes some basic assumptions about the IR it's been given. In particular, if there is only one 'invoke' in the function, then that invoke won't be going away. However, with the advent of the `llvm.donothing' intrinsic, those invokes may go away. If all of them go away, the landing pad no longer has any users. This confuses the back-end, which asserts. This happens with SjLj exceptions, because that's the model that modifies the IR based on there being invokes, etc. in the function. Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will give us a CFG that the back-end won't be confused about. If all of the invokes in a function are removed, then the SjLj EH prepare pass won't insert the bogus code the relies upon the invokes being there. <rdar://problem/13228754&13316637> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Upgrade tests to the latest debug info format.David Blaikie
Mostly this is just changing the named metadata (llvm.dbg.sp, llvm.dbg.gv, llvm.dbg.<func>.lv, etc -> llvm.dbg.cu), adding a few fields to older records (DIVariable: flags/inlined-at, DICompileUnit: sp/gv/types, DISubprogram: local variables list) The tests to update were discovered by a change I'm working on to remove debug info version support - so any tests using old debug info versions I haven't updated probably are bad tests or just not actually designed to test debug info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176671 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07[fast-isel] Add support for the expect intrinsic.Chad Rosier
rdar://13370942 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176649 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02ARM NEON: Fix v2f32 float intrinsicsArnold Schwaighofer
Mark them as expand, they are not legal as our backend does not match them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Generate an error message instead of asserting or segfaulting when we can'tChad Rosier
handle indirect register inputs. rdar://13322011 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176367 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Add support for using non-pic code for arm and thumb1 when emitting the sjljChad Rosier
dispatch code. As far as I can tell the thumb2 code is behaving as expected. I was able to compile and run the associated test case for both arm and thumb1. rdar://13066352 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-27ARM: FMA is legal only if VFP4 is available.Jim Grosbach
rdar://13306723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-27SelectionDAG: If llvm.donothing has a landingpad, we should clearManman Ren
CurrentCallSite to avoid an assertion failure: assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); rdar://problem/13228754 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176154 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls
instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20DAGCombiner: Fold pointless truncate, bitcast, buildvector seriesArnold Schwaighofer
(2xi32) (truncate ((2xi64) bitcast (buildvector i32 a, i32 x, i32 b, i32 y))) can be folded into a (2xi32) (buildvector i32 a, i32 b). Such a DAG would cause uneccessary vdup instructions followed by vmovn instructions. We generate this code on ARM NEON for a setcc olt, 2xf64, 2xf64. For example, in the vectorized version of the code below. double A[N]; double B[N]; void test_double_compare_to_double() { int i; for(i=0;i<N;i++) A[i] = (double)(A[i] < B[i]); } radar://13191881 Fixes bug 15283. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175670 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19ARM NEON: Merge a f32 bitcast of a v2i32 extracteltArnold Schwaighofer
A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18Comment out the rdar number.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18[fast-isel] Remove an invalid assert.Chad Rosier
If the memcpy has an odd length with an alignment of 2, this would incorrectly assert on the last 1 byte copy. rdar://13202135 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao
inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13temporarily revert the patch due to some conflictsWeiming Zhao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao
on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-06-30 12:03:27 +0000