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2012-03-20Fix test case from r153135.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153140 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov
Patch by Weiming Zhao! This fixes PR12212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[fast-isel] Address Eli's comments for r152847. Specifically, add a test caseChad Rosier
and still allow immediate encoding, just not with cmn. rdar://11038907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15ARM case-insensitive checking for APSR_nzcv.Jim Grosbach
rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints onLang Hames
register allocation by allowing all 32 D-registers to be used. Patch by Cameron Zwarich. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng
(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng
performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen
When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames
The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05updated patch for the ARM fused multiply add/subSebastian Pop
In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen
MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Do trivial CSE of dead BBs during codegen preparation.Bill Wendling
Some BBs can become dead after codegen preparation. If we delete them here, it could help enable tail-call optimizations later on. <rdar://problem/10256573> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03Fix RA-dependent test.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Neuter the optimization I implemented with r107852 and r108258 which turn someEvan Cheng
floating point equality comparisons into integer ones with -ffast-math. The issue is the optimization causes +0.0 != -0.0. Now the optimization is only done when one side is known to be 0.0. The other side's sign bit is masked off for the comparison. rdar://10964603 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Revert r151816 as Jim has the appropriate fix.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix testcases from r151807.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Add missing triple for tests.Jim Grosbach
Make darwin bots happier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ↵James Molloy
though they could have sideeffects. Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar
prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Handle regmasks in MachineCSE.Jakob Stoklund Olesen
Don't attempt to extend physreg live ranges across calls. <rdar://problem/10942095> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24test commit. removing unnecessary whitespace.Kristof Beyls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Thumb2 size reduction fix for tied operands of tMUL.Jim Grosbach
The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman
bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151310 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Make tests less sensitive to scheduling changes.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Fix to make sure that a comdat group gets generated correctly for a static ↵Anton Korobeynikov
member of instantiated C++ templates. Patch by Kristof Beyls! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bitsEvan Cheng
of x are zero. This optimizes rev + lsr 16 to rev16. rdar://10750814 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17[fast-isel] Add support for returning non-legal types with no sign- or zero-Chad Rosier
entend flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky
run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Tighten physical register invariants: Allocatable physical registers canLang Hames
only be live in to a block if it is the function entry point or a landing pad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08[fast-isel] Add support for SUBs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Add comment to test case.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08[fast-isel] Add support for ORs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07[fast-isel] Add support for indirect branches.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06[fast-isel] Add support for ADDs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for selecting UIToFP.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for ↵NAKAMURA Takumi
now. It requires TARGETS=arm. I cannot reproduce a fixed issue with other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Replace the use of isPredicable() with isPredicated() inChad Rosier
MachineBasicBlock::canFallThrough(). We're interested in the state of the instruction (i.e., is this a barrier or not?), not if the instruction is predicable or not. rdar://10501092 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Clear kill flags before propagating a copy.Jakob Stoklund Olesen
The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Improve sub-register def handling in ProcessImplicitDefs.Jakob Stoklund Olesen
This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov
and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen
A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov
This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth
violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
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