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2012-11-14Fix nacl.read.tp() intrinsic to not generate "addl %gs:0, %REG"Mark Seaborn
NaCl only allows using "mov" with a %gs prefix. The fix requires generating the mov instruction using a custom inserter that calls BuildMI(). Also convert the intrinsic's tests to use -filetype=asm rather than -filetype=obj. This avoids some limitations of llvm-objdump and is the more normal way to write LLVM tests. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2837 TEST="llvm-lit test/NaCl" Review URL: https://codereview.chromium.org/11410058
2012-11-15InstCombineAndOrXor.cpp: Escape bracket in doxygen description. ↵NAKAMURA Takumi
[-Wdocumentation] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168013 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Add doInitialization and doFinalization methods to ModulePass's, to allow ↵Owen Anderson
them to be re-initialized and reused on multiple Module's. Patch by Pedro Artigas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove unneeded #includes.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Use reserve() to avoid vector reallocation.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove the CellSPU port.Eric Christopher
Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix invalid asserts, use llvm_unreachable instead.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Added multiclass for post-increment load instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14canJoinPhys method doesn't modify CoalescerPair. Make it const.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove dead code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167970 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove DOS line endings.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer
bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Replace std::vector -> SmallVector in BBVectorizeHal Finkel
For now, this uses 8 on-stack elements. I'll need to do some profiling to see if this is the best number. Pointed out by Jakob in post-commit review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem
is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14[NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski
Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix really stupid ARM EHABI info generation bug: we should not emitAnton Korobeynikov
eh table and handler data if there are no landing pads in the function. Patch by Logan Chien with some cleanups from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix the largest offender of determinism in BBVectorizeHal Finkel
Iterating over the children of each node in the potential vectorization plan must happen in a deterministic order (because it affects which children are erased when two children conflict). There was no need for this data structure to be a map in the first place, so replacing it with a vector is a small change. I believe that this was the last remaining instance if iterating over the elements of a Dense* container where the iteration order could matter. There are some remaining iterations over std::*map containers where the order might matter, but so long as the Value* for instructions in a block increase with the order of the instructions in the block (or decrease) monotonically, then this will appear to be deterministic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167942 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Use __aeabi_read_tp for non-naclDavid Sehr
Fixes an introduced if statement to use the upstream version when other than nacl targets are used. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11410094
2012-11-14X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach
When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14s/assert/llvm_unreachable/Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Rename NotNaCl to IsNotNacl, for consistency with other similarly-named ↵JF Bastien
predicates. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/11361253
2012-11-14Implement sandboxing of NEON store instructionsEli Bendersky
BUG=http://code.google.com/p/nativeclient/issues/detail?id=3124 Review URL: https://codereview.chromium.org/11361249
2012-11-14[TSan] fix indentationAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167928 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Emit relocations from .debug_aranges to .debug_info for asm filesAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Revert some redundant parts of r142605.Patrik Hägglund
This seems like redundant leftovers from r142288 - exposing TargetData::parseSpecifier to LLParser - which got reverted. Removes redunant td != NULL checks in parseSpecifier, and simplifies the interface to parseSpecifier and init. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Set FFLOOR of vectors to expand to keep intruction selection from failing.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Factor out an overly replicated typecast. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Set FFLOOR for vectors to expand on CellSPU to keep instruction selection ↵Craig Topper
from failing on llvm.floor of a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Add newlines to end of debug messages.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167913 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
Conflicts: lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix thumb2 jump relocation testDavid Sehr
Enable return address stack feature Use DwarfCFI only for NaCl BUG= http://code.google.com/p/nativeclient/issues/detail?id=3124 TEST=thumb_jump24_fixup.ll Review URL: https://codereview.chromium.org/11360241
2012-11-14Fix broken asserts. Also, spell 'indices' correctly.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14[Object] Fix endianess bug by refactoring Archive::Symbol::getMember.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167893 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14use the getSplat API. Patch by Paul Redmond.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167892 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher
temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert -join-splitedges to a boolean cmd line option.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13The MachineScheduler does not currently require JoinSplitEdges.Andrew Trick
This option will eventually either be enabled unconditionally or replaced by a more general live range splitting optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13[MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Add (some) PowerPC TLS relocation types to ELF.h andUlrich Weigand
generate them from PPCELFObjectWriter::getRelocTypeInner as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix wrong PowerPC instruction opcodes for:Ulrich Weigand
- lwaux - lhzux - stbu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix wrong PowerPC instruction encodings due toUlrich Weigand
operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix instruction encoding for "bd(n)z" on PowerPC,Ulrich Weigand
by using a new instruction format BForm_1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix instruction encoding for "isel" on PowerPC,Ulrich Weigand
using a new instruction format AForm_4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren
chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Do not consider a machine instruction that uses and defines the sameUlrich Weigand
physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Adding changes to support GNU style archive library readingShankar Easwaran
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167853 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix -join-splitedges: my previous "cleanup" broke it.Andrew Trick
Working on reducing unit tests. This won't be enabled unless a subtarget enables misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167851 91177308-0d34-0410-b5e6-96231b3b80d8
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