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2013-02-14[mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka
1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14BBVectorize: Remove the remaining instances of std::multimapHal Finkel
All instances of std::multimap have now been replaced by DenseMap<K, std::vector<V> >, and this yields a speedup of 5% on the csa.ll test case from PR15222. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14BBVectorize: Don't store candidate pairs in a std::multimapHal Finkel
This is another commit on the road to removing std::multimap from BBVectorize. This gives an ~1% speedup on the csa.ll test case in PR15222. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Simplify code. Remove "else after return".Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Update comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Hexagon: Change insn class to support instruction encoding.Jyotsna Verma
This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14s/bool/LLVMBool/Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Add two new functions to the C API:Bill Wendling
LLVMCreateMemoryBufferWithMemoryRange - exposes MemoryBuffer::getMemBuffer LLVMCreateMemoryBufferWithMemoryRangeCopy - exposes MemoryBuffer::getMemBufferCopy Patch by Moritz Maxeiner! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14added basic support for Intel ADX instructionsKay Tiong Khoo
-feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600/SI: Fix int_SI_fs_interp_constantMichel Danzer
The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-1480-colNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma
This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao
inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune
It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Export instructions are no longer terminatorVincent Lejeune
This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Fold zero/one in export instructionsVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold modifier/litterals in vector instVincent Lejeune
This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175173 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: stop claiming that NEON registers are usable for now.Tim Northover
If vector types have legal register classes, then LLVM bypasses LegalizeTypes on them, which causes faults currently since the code to handle them isn't in place. This fixes test failures when AArch64 is the default target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: add block comments where missingTim Northover
Only comments affected. No code change at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Workaround an MSan false positive.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Add some legality checks for SETCC before introducing it in the DAG combiner ↵Owen Anderson
post-operand legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky
Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer
Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175139 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14RegisterCoalescer::reMaterializeTrivialDef() can constrain the destinationCameron Zwarich
register class to match the defining instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Teach the DataLayout aware constant folder to be much more aggressive towardsNick Lewycky
'and' instructions. This is a pattern that shows up a lot in ubsan binaries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Remove the form field from Mips16 instruction formats and set thingsReed Kotler
up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fix RegisterCoalescer::rematerializeTrivialDef() so that it works on flippedCameron Zwarich
CoalescerPairs. Also, make it take a CoalescerPair directly like other methods of RegisterCoalescer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fix some issues with rematerialization in RegisterCoalescer when the destinationCameron Zwarich
of the copy is a subregister def. The current code assumes that it can do a full def of the destination register, but it is not checking that the def operand is read-undef. It also doesn't clear the subregister index of the destination in the new instruction to reflect the full subregister def. These issues were found running 'make check' with my next commit that enables rematerialization in more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Don't assume the mangling of static functions.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Don't asume that a static function in an extern "C" block will not be mangled.Rafael Espindola
Since functions with internal linkage don't have language linkage, it is valid to overload them: extern "C" { static int foo(); static int foo(int); } So we mangle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13temporarily revert the patch due to some conflictsWeiming Zhao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Retain the name of the new internal global that's been shrunk.Bill Wendling
It's possible (e.g. after an LTO build) that an internal global may be used for debugging purposes. If that's the case appending a '.b' to it makes it hard to find that variable. Steal the name from the old GV before deleting it so that they can find that variable again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13R600: Add support for 128-bit parametersTom Stellard
NOTE: This is a candidate for the Mesa stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Don't build tail calls to functions with three inreg arguments on x86-32 PIC.Nick Lewycky
Fixes PR15250! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175092 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao
on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma
instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline-asm] Add support for memory references that have non-immediateChad Rosier
displacements. rdar://12974533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline asm] Add a comment about the determinism of the rewrite sort.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13LoopVectorize: Simplify code for clarity.Benjamin Kramer
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Clean up LDV, no functionality change.Manman Ren
Remove dead functions: renameRegister Move private member variables from LDV to Impl Remove ssp/uwtable from testing case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline-asm] Use an array_pod_sort, rather than a std:sort.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Metadata for annotating loops as parallel. The first consumer for this Pekka Jaaskelainen
metadata is the loop vectorizer. See the documentation update for more info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175060 91177308-0d34-0410-b5e6-96231b3b80d8
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