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2013-03-31There is no longer any need to silence this compiler warning as the warning hasDuncan Sands
been turned off globally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfoHal Finkel
ImmToIdxMap should be a DenseMap (not a std::map) because there is no ordering requirement. Also, we don't need a separate list of instructions for noImmForm in eliminateFrameIndex, because this list is essentially the complement of the keys in ImmToIdxMap. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.Benjamin Kramer
A vector sext + sitofp is a lot cheaper than 8 scalar conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31Add the PPC lfiwax instructionHal Finkel
This instruction is available on modern PPC64 CPUs, and is now used to improve the SINT_TO_FP lowering (by eliminating the need for the separate sign extension instruction and decreasing the amount of needed stack space). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31Cleanup PPC(64) i32 -> float/double conversionHal Finkel
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled because it relied on broken EXTSW_32/STD_32 instruction definitions. The original intent had been to enable these 64-bit instructions to be used on CPUs that support them even in 32-bit mode. Unfortunately, this form of lying to the infrastructure was buggy (as explained in the FIXME comment) and had therefore been disabled. This re-enables this functionality, using regular DAG nodes, but only when compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead) are removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30DAGCombine: visitXOR can replace a node without returning it, bail out in ↵Benjamin Kramer
that case. Fixes the crash reported in PR15608. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Change '@SECREL' suffix to GAS-compatible '@SECREL32'.Benjamin Kramer
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'. With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here). Patch by David Nadlinger! Differential Revision: http://llvm-reviews.chandlerc.com/D429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Put private class into an anonmyous namespace.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[NVPTX] Add NVVMReflect pass to allow compile-time selection ofJustin Holewinski
specific code paths. This allows us to write code like: if (__nvvm_reflect("FOO")) // Do something else // Do something else and compile into a library, then give "FOO" a value at kernel compile-time so the check becomes a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[NVPTX] Run clang-format on all NVPTX sources.Justin Holewinski
Hopefully this resolves any outstanding style issues and gives us an automated way of ensuring we conform to the style guidelines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Implement XOR reassociation. It is based on following rules:Shuxin Yang
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2), only useful when c1=c2 rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2)) rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2 rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2 It reduces an application's size (in terms of # of instructions) by 8.9%. Reviwed by Pete Cooper. Thanks a lot! rdar://13212115 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Add patterns for DSP indexed load instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Define reg+imm load/store pattern templates.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka
Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Remove unused variables.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Move the code which does dag-combine for multiply-add/sub nodes toAkira Hatanaka
derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka
The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30Fix indentation.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Add mips-specific nodes which will be used to select multiply and divideAkira Hatanaka
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function isAkira Hatanaka
called in several places in ScheduleDAGRRList.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStackAkira Hatanaka
to handle accumulator registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Expand pseudo load, store and copy instructions right beforeAkira Hatanaka
callee-saved scan. The code makes use of register's scavenger's capability to spill multiple registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30[mips] Define pseudo instructions for spilling and copying accumulatorAkira Hatanaka
registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29PNaCl: Fix ExpandTls to handle a couple of corner cases involving PHI nodesMark Seaborn
ExpandTls's use of replaceUsesOfWith() didn't work for PHI nodes containing the same Constant twice (which needs to work for same or differing incoming BasicBlocks). The same applies to ExpandTlsConstantExpr. I noticed this while implementing ExpandConstantExpr. Fix this and factor out some common code that all three passes can use. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2837 TEST=test/Transforms/NaCl/*.ll Review URL: https://codereview.chromium.org/13128002
2013-03-29Use SmallVectorImpl instead of SmallVector at the uses.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29SmallVector and SmallPtrSet allocations now power-of-two aligned.Jean-Luc Duprat
This time tested on both OSX and Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178377 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Add clang.arc.used to ModuleHasARC so ARC always runs if said call is ↵Michael Gottesman
present in a module. clang.arc.used is an interesting call for ARC since ObjCARCContract needs to run to remove said intrinsic to avoid a linker error (since the call does not exist). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Hexagon: Add emitFrameIndexDebugValue function to emit debug information.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178368 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Use 12 as the magic number for our abbreviation data and ourEric Christopher
die values. A lot of DIEs have 10 attributes in C++ code (example clang), none had more than 12. Seems like a good default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Move the construction of the skeleton compile unit after theEric Christopher
entire original compile unit has been constructed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Implement FRINT lowering on PPC using frinHal Finkel
Like nearbyint, rint can be implemented on PPC using the frin instruction. The complication comes from the fact that rint needs to set the FE_INEXACT flag when the result does not equal the input value (and frin does not do that). As a result, we use a custom inserter which, after the rounding, compares the rounded value with the original, and if they differ, explicitly sets the XX bit in the FPSCR register (which corresponds to FE_INEXACT). Once LLVM has better modeling of the floating-point environment we should be able to (often) eliminate this extra complexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29[mips] Define a function which returns the GPR register class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178359 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Build fixes for STLPort + GCCMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Fix loop styleMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Remove the old CodePlacementOpt pass.Benjamin Kramer
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Fix a typoNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Hexagon: Disable DwarfUsesInlineInfoSection flag.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178345 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Add PPC FP rounding instructions fri[mnpz]Hal Finkel
These instructions are available on the P5x (and later) and on the A2. They implement the standard floating-point rounding operations (floor, trunc, etc.). One caveat: frin (round to nearest) does not implement "ties to even", and so is only enabled in fast-math mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Revert "Fix allocations of SmallVector and SmallPtrSet so they are more ↵Rafael Espindola
prone to" This reverts commit 617330909f0c26a3f2ab8601a029b9bdca48aa61. It broke the bots: /home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:150: PushPopTest /home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:118: Failure Value of: v[i].getValue() Actual: 0 Expected: value Which is: 2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Fix allocations of SmallVector and SmallPtrSet so they are more prone toJean-Luc Duprat
being power-of-two sized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178332 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Removed trailing whitespace.Michael Gottesman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178329 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29[mips] Change type of accumulator registers to Untyped. Add two more accumulatorAkira Hatanaka
register classes for Mips64 and DSP-ASE. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29[mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka
No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29[mips] Add parameter Alignment to MipsFrameLowering's constructor.Akira Hatanaka
No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Add a pass to strip bitcode metadata.Jan Voung
This only works on instruction attachments for now. Since it is a ModulePass we can add something to strip NamedMetadata based on a whitelist, if we want to retain some of that. It does not touch debug metadata, and leaves -strip-debug to handle that. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3348 Review URL: https://codereview.chromium.org/12844027
2013-03-28[Mips Assembler] Add support for OR macro with imediate opperandJack Carter
Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Add support of RDSEED defined in AVX2 extensionMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Enhance boolean simplification to handle 16-/64-bit RDRANDMichael Liao
- RDRAND always clears the destination value when a random value is not available (i.e. CF == 0). This value is truncated or zero-extended as the false boolean value to be returned. Boolean simplification needs to skip this 'zext' or 'trunc' node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
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