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2013-04-11Add CLAC/STAC instruction encoding/decoding supportMichael Liao
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Enhance bool simplifcation in X86 to handle more casesMichael Liao
This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Fix MachO's getRelocationAdditionalInfo.Rafael Espindola
It was returning the loaded address of the section containing the relocation, which really doesn't seem to be the intent of this function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Make PPCInstrInfo::isPredicated always return falseHal Finkel
Because of how predication in implemented on PPC (only for branches), I think that this is the right thing to do. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179252 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[MIPS] Fix LLVM issues with recent LLVM trunk mergePetar Jovanovic
This change fixes some of the issues that came with recent merge with LLVM trunk, and it removes some workarounds that are not needed anymore in the code. In more details, it: - removes hack to set ELF::EF_MIPS_PIC flag; - checks whether __nacl_read_tp is defined in the module, as different relocation(s) is used to calculate the address; - marks Mips::JALRPseudo as indirect call in NaCl rewrite pass; - fixes incorrect merge in MipsAsmPrinter.cpp and MipsMCTargetDesc.cpp. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2275 TEST= run smoke tests Review URL: https://codereview.chromium.org/13601014
2013-04-10MC: Support COFF image-relative MCSymbolRefsNico Rieck
Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Manually remove successors in if conversion when CopyAndPredicateBlock is usedHal Finkel
In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10No need to have this return a bool.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Track the compact unwind encoding for when we are unable to generate compact ↵Bill Wendling
unwind information. Compact unwind has an encoding for when we're not able to generate compact unwind and must generate an EH frame instead. Track that, but still emit that CU encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10fixed to disassemble with tab after mnemonic rather than spaceKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10In the X86 back end, getMemoryOperandNo() returns the offsetPreston Gurd
into the operand array of the start of the memory reference descriptor. Additional code in EncodeInstruction provides an additional adjustment. This patch places that additional code in a separate function, called getOperandBias, so that any caller of getMemoryOperandNo can also call getOperandBias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179211 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Tidy up, fix and simplify a few of the SMLocs. Prior to r179109 the Start SMLocChad Rosier
wasn't always the start of the operand. If there was a symbol reference, then Start pointed to that token. It's very likely there are other places that need to be updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179210 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Make the SLP store-merger less paranoid about function calls. We check for ↵Nadav Rotem
function calls when we check if it is safe to sink instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10We require DataLayout for analyzing the size of stores.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179206 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Remove unused variable.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10PPC: Don't predicate a diamond with two counter decrementsHal Finkel
I've not seen this happen in practice, and probably can't until we start allowing decrement-counter-based conditional branches to be double predicated, but just in case, don't allow predication of a diamond in which both sides have ctr-defining branches. Even though the branching behavior of these can be predicated, the counter-decrementing behavior cannot be. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Reapply r179115, but use parsePrimaryExpression a little more judiciously.Chad Rosier
Test cases that regressed due to r179115, plus a few more, were added in r179182. Original commit message below: [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to parse an identifier. Otherwise, parseExpression may parse multiple tokens, which makes it impossible to properly compute an immediate displacement. An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in the below example: __asm mov eax, [Symbol + ImmDisp] Part of rdar://13611297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: Add pattern for AMDGPUurecipMichel Danzer
21 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10This is for an experimental option -mips-os16. The idea is to compile allReed Kotler
Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Use a scheme closer to that of GNU as when deciding the type of aPeter Collingbourne
symbol with multiple .type declarations. Differential Revision: http://llvm-reviews.chandlerc.com/D607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10PNaCl ABI checker: Disallow the GetElementPtr instructionMark Seaborn
This instruction is removed by ExpandGetElementPtr. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3343 TEST=test/NaCl/PNaClABI/instructions.ll + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/14071005
2013-04-10PNaCl ABI checker: Disallow "section", "thread_local" and "gc" attributesMark Seaborn
* Disallow "section" on functions and global variables. * Disallow "thread_local" on global variables. * Disallow "gc" on functions. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2837 BUG= https://code.google.com/p/nativeclient/issues/detail?id=3126 TEST=test/NaCl/PNaClABI/global-attributes.ll + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/14063007
2013-04-10Template MachOObjectFile over endianness too.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Change CloneFunctionInto to always clone Argument attributes induvidually,Joey Gouly
rather than checking if the source and destination have the same number of arguments and copying the attributes over directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: dynamical figure out the reg class of MIMGChristian Konig
Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: adjust writemask to only the used componentsChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: remove image sample writemaskChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Cleanup PPCInstrInfo::DefinesPredicateHal Finkel
Implement suggestions made by Bill Schmidt in post-commit review. Thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10RegionInfo: Add helpers to replace entry/exit recursivelyTobias Grosser
Contributed by: Star Tan <tanmx_star@yeah.net> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10PPC: Prep for if conversion of bctr[l]Hal Finkel
This adds in-principle support for if-converting the bctr[l] instructions. These instructions are used for indirect branching. It seems, however, that the current if converter will never actually predicate these. To do so, it would need the ability to hoist a few setup insts. out of the conditionally-executed block. For example, code like this: void foo(int a, int (*bar)()) { if (a != 0) bar(); } becomes: ... beq 0, .LBB0_2 std 2, 40(1) mr 12, 4 ld 3, 0(4) ld 11, 16(4) ld 2, 8(4) mtctr 3 bctrl ld 2, 40(1) .LBB0_2: ... and it would be safe to do all of this unconditionally with a predicated beqctrl instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Template the MachO types over endianness.Rafael Espindola
For now they are still only used as little endian. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10__sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not inEvan Cheng
xmm0 / xmm1. rdar://13599493 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Generalize the PassConfig API and remove addFinalizeRegAlloc().Andrew Trick
The target hooks are getting out of hand. What does it mean to run before or after regalloc anyway? Allowing either Pass* or AnalysisID pass identification should make it much easier for targets to use the substitutePass and insertPass APIs, and create less need for badly named target hooks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Mips specific inline asm operand modifier 'D' Jack Carter
Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Allow PPC B and BLR to be if-converted into some predicated formsHal Finkel
This enables us to form predicated branches (which are the same conditional branches we had before) and also a larger set of predicated returns (including instructions like bdnzlr which is a conditional return and loop-counter decrement all in one). At the moment, if conversion does not capture all possible opportunities. A simple example is provided in early-ret2.ll, where if conversion forms one predicated return, and then the PPCEarlyReturn pass picks up the other one. So, at least for now, we'll keep both mechanisms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Fix some comment typos.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179132 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Cleanup. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Cleanup. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Remove unused method and default values.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Revert r179115 as it looks to have killed the ASan tests.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Rationalize the formatting of these case labels. Having two sortedChandler Carruth
columns is essentially impossible to edit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler
and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Add support for bottom-up SLP vectorization infrastructure.Nadav Rotem
This commit adds the infrastructure for performing bottom-up SLP vectorization (and other optimizations) on parallel computations. The infrastructure has three potential users: 1. The loop vectorizer needs to be able to vectorize AOS data structures such as (sum += A[i] + A[i+1]). 2. The BB-vectorizer needs this infrastructure for bottom-up SLP vectorization, because bottom-up vectorization is faster to compute. 3. A loop-roller needs to be able to analyze consecutive chains and roll them into a loop, in order to reduce code size. A loop roller does not need to create vector instructions, and this infrastructure separates the chain analysis from the vectorization. This patch also includes a simple (100 LOC) bottom up SLP vectorizer that uses the infrastructure, and can vectorize this code: void SAXPY(int *x, int *y, int a, int i) { x[i] = a * x[i] + y[i]; x[i+1] = a * x[i+1] + y[i+1]; x[i+2] = a * x[i+2] + y[i+2]; x[i+3] = a * x[i+3] + y[i+3]; } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09[ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need toChad Rosier
parse an identifier. Otherwise, parseExpression may parse multiple tokens, which makes it impossible to properly compute an immediate displacement. An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in the below example: __asm mov eax, [Symbol + ImmDisp] The existing test cases exercise this patch. rdar://13611297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179115 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09The .dwo section shouldn't contain the unrelocated values (andEric Christopher
therefore not at all) of the pc or statement list. We also don't need to emit the compilation dir so save so space and time and don't bother. Fix up the testcase accordingly and verify that we don't emit the attributes or the items that they use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179114 91177308-0d34-0410-b5e6-96231b3b80d8
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