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2012-12-11Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund
instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund
EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund
EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund
Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11[CMake] Remove dependencies to intrinsics_gen I introduced in r169724.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Fix PR14565. Don't if-convert loops that have switch statements in them.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Stylistic tweak.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Fix a miscompile in the DAG combiner. Previously, we would incorrectlyChandler Carruth
try to reduce the width of this load, and would end up transforming: (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32) to (truncate (zextload i32 <ptr+4> as i64) to i32) We lost the sext attached to the load while building the narrower i32 load, and replaced it with a zext because lshr always zext's the results. Instead, bail out of this combine when there is a conflict between a sextload and a zext narrowing. The rest of the DAG combiner still optimize the code down to the proper single instruction: movswl 6(...),%eax Which is exactly what we wanted. Previously we read past the end *and* missed the sign extension: movl 6(...), %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Fall back to the selection dag isel to select tail calls.Chad Rosier
This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Refactor out the abbreviation handling into a separate class thatEric Christopher
controls each of the abbreviation sets (only a single one at the moment) and computes offsets separately as well for each set of DIEs. No real function change, ordering of abbreviations for the skeleton CU changed but only because we're computing in a separate order. Fix the testcase not to care. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Some enhancements for memcpy / memset inline expansion.Evan Cheng
1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Optimistically analyse Phi cyclesArnold Schwaighofer
Analyse Phis under the starting assumption that they are NoAlias. Recursively look at their inputs. If they MayAlias/MustAlias there must be an input that makes them so. Addresses bug 14351. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Defer call to InitSections until after MCContext has been initialized. IfLang Hames
InitSections is called before the MCContext is initialized it could cause duplicate temporary symbols to be emitted later (after context initialization resets the temporary label counter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Rearrange vars and make comments more obvious.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Remove blank line at top of file.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Fix a coding style nit.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169776 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Enable the loop vectorizer only on O2 and above. (Still disabled by default)Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10LegalizeDAG: Allow type promotion of scalar loadsTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10LegalizeDAG: Allow type promotion for scalar storesTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Split the LoopVectorizer into H and CPP.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Cleanup formatting, comments and naming.Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10[mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Use the somewhat semantic term "split dwarf" it more matches what'sEric Christopher
going on and makes a lot of the terminology in comments make more sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Delete the FissionCU.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Reorder fission variables.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Don't use a red zone for code coverage if the user specified `-mno-red-zone'.Bill Wendling
The `-mno-red-zone' flag wasn't being propagated to the functions that code coverage generates. This allowed some of them to use the red zone when that wasn't allowed. <rdar://problem/12843084> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Add support for reverse induction variables. For example:Nadav Rotem
while (i--) sum+=A[i]; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169752 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10This patch adds statistics for other non-DWARF fragments emitted byEli Bendersky
the assembler. This is useful in order to know how the numbers add up, since in particular the Align fragments account for a non-trivial portion of the emitted fragments (especially on -O0 which sets relax-all). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Use GetUnderlyingObjects in mischedHal Finkel
misched used GetUnderlyingObject in order to break false load/store dependencies, and the -enable-aa-sched-mi feature similarly relied on GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis. Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so (especially due to LSR) all of these mechanisms failed for induction-variable-dependent loads and stores inside loops. This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects (which will recurse through phi and select instructions) in misched. Andy reviewed, tested and simplified this patch; Thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth
Accidental commit... git svn betrayed me. Sorry for the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth
Summary: Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Fix a typo in my previous commit -- bloomfield is 0x1A not 0x2A.Chandler Carruth
Thanks to the PaX folks for noticing in review! We need some tests here, any sugestions welcome... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169739 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth
Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Add a new visitor for walking the uses of a pointer value.Chandler Carruth
This visitor provides infrastructure for recursively traversing the use-graph of a pointer-producing instruction like an alloca or a malloc. It maintains a worklist of uses to visit, so it can handle very deep recursions. It automatically looks through instructions which simply translate one pointer to another (bitcasts and GEPs). It tracks the offset relative to the original pointer as long as that offset remains constant and exposes it during the visit as an APInt offset. Finally, it performs conservative escape analysis. However, currently it has some limitations that should be addressed going forward: 1) It doesn't handle vectors of pointers. 2) It doesn't provide a cheaper visitor when the constant offset tracking isn't needed. 3) It doesn't support non-instruction pointer values. The current functionality is exactly what is required to implement the SROA pointer-use visitors in terms of this one, rather than in terms of their own ad-hoc base visitor, which was always very poorly specified. SROA has been converted to use this, and the code there deleted which this utility now provides. Technically speaking, using this new visitor allows SROA to handle a few more cases than it previously did. It is now more aggressive in ignoring chains of instructions which look like they would defeat SROA, but in fact do not because they never result in a read or write of memory. While this is "neat", it shouldn't be interesting for real programs as any such chains should have been removed by others passes long before we get to SROA. As a consequence, I've not added any tests for these features -- it shouldn't be part of SROA's contract to perform such heroics. The goal is to extend the functionality of this visitor going forward, and re-use it from passes like ASan that can benefit from doing a detailed walk of the uses of a pointer. Thanks to Ben Kramer for the code review rounds and lots of help reviewing and debugging this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Teach DAG combine to handle vector add/sub with vectors of all 0s.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10[CMake] Update dependencies to intrinsics_gen corresponding to r169711.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Fix PR14548: SROA was crashing on a mixture of i1 and i8 loads and stores.Chandler Carruth
When SROA was evaluating a mixture of i1 and i8 loads and stores, in just a particular case, it would tickle a latent bug where we compared bits to bytes rather than bits to bits. As a consequence of the latent bug, we would allow integers through which were not byte-size multiples, a situation the later rewriting code was never intended to handle. In release builds this could trigger all manner of oddities, but the reported issue in PR14548 was forming invalid bitcast instructions. The only downside of this fix is that it makes it more clear that SROA in its current form is not capable of handling mixed i1 and i8 loads and stores. Sometimes with the previous code this would work by luck, but usually it would crash, so I'm not terribly worried. I'll watch the LNT numbers just to be sure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09Reorganize FastMathFlags to be a wrapper around unsigned, and streamline ↵Michael Ilseman
some interfaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09LoopVectorize: support vectorizing intrinsic callsPaul Redmond
- added function to VectorTargetTransformInfo to query cost of intrinsics - vectorize trivially vectorizable intrinsic calls such as sin, cos, log, etc. Reviewed by: Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09Have the bitcode reader/writer just use FPMathOperator's fast math enum directlyMichael Ilseman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169710 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09test commit.Paul Redmond
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09Use m_OneUse pattern instead of hasOneUse() method.Jakub Staszak
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09Remove trailing spaces.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09Switch SROA to pop Uses off the back of its visitors' queues.Chandler Carruth
This will more closely match the behavior of the new PtrUseVisitor that I am adding. Hopefully this will not change the actual behavior in any way, but by making the processing order more similar help in debugging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169697 91177308-0d34-0410-b5e6-96231b3b80d8
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