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2012-02-13Fix various issues (or do cleanups) found by enabling certain MSVC warnings.Ahmed Charles
- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default. - Remove misplaced llvm_unreachable. - Add static to a declaration of a function on MSVC x86 only. - Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Remove more vector_shuffle patterns for unpack. These should be target ↵Craig Topper
specific nodes when they get to isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Recommit r150328. Previous test failures should be fixed by r150360.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only ↵Craig Topper
have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Revert r150328, "Remove more vector_shuffle patterns."NAKAMURA Takumi
It caused 3 failures on pre-penryn and non-x86(generic) hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fixed bug when custom lowering DEC64m on x86.Pete Cooper
If the DEC node had more than one user, it was doing this lowering but leaving the original DEC node around and so decrementing twice. Fixes PR11964. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12This patch addresses the problem of poor code generation for the zextNadav Rotem
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12StringSwitchify the rest of Triple.cpp.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150332 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Switch a bunch of manual if-chains to use StringSwitch. Clean them up inChandler Carruth
the process. Some of these are still a bit gross. Still, this cuts 80 some lines out of this ridiculous file. ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Remove more vector_shuffle patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Expose the ELFObjectFile class directly in the Object/ELF.h header, similarlyEli Bendersky
to what's done for MachO and COFF. This allows advanced uses of the class to be implemented outside the Object library. In particular, the DyldELFObject subclass is now moved into its logical home - ExecutionEngine/RuntimeDyld. This patch was reviewed by Michael Spencer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Handle InvokeInst in EvaluateBlock. Don't try to support exceptions, it's justNick Lewycky
that no optz'ns have run yet to convert invokes to calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12false is totally null!Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI callsNick Lewycky
to TargetLibraryInfo and use one of them in GlobalOpt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Pass TargetData and TargetLibraryInfo through to the constant folder. Fixes aNick Lewycky
few fixme's when TLI was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Remove more vector_shuffle patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Fix function name in comment to match actual name. Fix comments that are usingNick Lewycky
doxy-style on local variables to not do so. Fix one 80-col violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12Don't traverse the PHI nodes twice. No functionality change!Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Remove more vector_shuffle patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150314 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov
Patch by Kai Nacke! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Don't mix declarations and code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Make the EDis tables const.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer
This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11[WIP] Initial code for module flags.Bill Wendling
Module flags are key-value pairs associated with the module. They include a 'behavior' value, indicating how module flags react when mergine two files. Normally, it's just the union of the two module flags. But if two module flags have the same key, then the resulting flags are dictated by the behaviors. Allowable behaviors are: Error Emits an error if two values disagree. Warning Emits a warning if two values disagree. Require Emits an error when the specified value is not present or doesn't have the specified value. It is an error for two (or more) llvm.module.flags with the same ID to have the Require behavior but different values. There may be multiple Require flags per ID. Override Uses the specified value if the two values disagree. It is an error for two (or more) llvm.module.flags with the same ID to have the Override behavior but different values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Remove some patterns for matching vector_shuffle instructions since ↵Craig Topper
vector_shuffles should be custom lowered before isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Add TargetPassConfig hooks for scheduling/bundling.Andrew Trick
In case the MachineScheduling pass I'm working on doesn't work well for another target, they can completely override it. This also adds a hook immediately after the RegAlloc pass to cleanup immediately after vregs go away. We may want to fold it into the postRA hook later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle ↵Craig Topper
mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Allow Post-RA LICM to hoist reserved register reads.Jakob Stoklund Olesen
When using register masks, registers like %rip are clobbered by the register mask. LICM should still be able to hoist instructions reading %rip from a loop containing calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150288 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Handle register masks in local live range splitting.Jakob Stoklund Olesen
Again the goal is to produce identical assembly with register mask operands enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Don't read PreRegAlloc before it is initialized.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Revert r150222, as the clang driver now handles this properly.Jim Grosbach
Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Add a static MachineOperand::clobbersPhysReg().Jakob Stoklund Olesen
It can be necessary to detach a register mask pointer from its MachineOperand. This method is convenient for checking clobbered physregs on a detached bitmask pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Add register mask support to InterferenceCache.Jakob Stoklund Olesen
This makes global live range splitting behave identically with and without register mask operands. This is not necessarily the best way of using register masks for live range splitting. It would be more efficient to first split global live ranges around calls (i.e., register masks), and reserve the fine grained per-physreg interference guidance for global live ranges that do not cross calls. For now the goal is to produce identical assembly when enabling register masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Remove unused variable.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Make valgrind happy.Jason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Update BBVectorize to use aliasesUnknownInst.Hal Finkel
This allows BBVectorize to check the "unknown instruction" list in the alias sets. This is important to prevent instruction fusing from reordering function calls. Resolves PR11920. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Have AliasSet::aliasesUnknownInst use pointer TBAA info when availableHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150249 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Fix PR11948: the result type of an icmp may be a vector of boolean -Duncan Sands
don't assume it is a boolean. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150247 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer
pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10comment grammarAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10unnecessary includeAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10PTX no longer needs to provide its own backend.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150227 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Remove unused 'isAlias' parameter.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach
rdar://10838899 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Constrain the regmask search space for local live ranges.Jakob Stoklund Olesen
When checking a local live range for interference, restrict the binary search to the single block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150220 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Cache basic block boundaries for faster RegMaskSlots access.Jakob Stoklund Olesen
Provide API to get a list of register mask slots and bits in a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150219 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Optimize LiveIntervals::intervalIsInOneMBB().Jakob Stoklund Olesen
No looping and binary searches necessary. Return a pointer to the containing block instead of just a bool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Cache iterators. Some of these are expensive to create.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150214 91177308-0d34-0410-b5e6-96231b3b80d8
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