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EmitValue (literal values). Previously only called on expressions in instructions. New test cases added to tls.s, tls-i386.s. Resolves PR11981.
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The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>
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used to incrementally update a created node without needing a
temporary node and RAUW.
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I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it.
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The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes.
A target has two ways of overriding standard passes:
1) Redefine the pass pipeline (override TargetPassConfig::add%Stage)
2) Replace or suppress individiual passes with TargetPassConfig::substitutePass.
In both cases, the command line options associated with the pass override the target default.
For example, say a target wants to disable machine instruction scheduling by default:
- The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods.
- Without any llc options, no scheduler is run.
- With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing.
Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day...
I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well.
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override specific passes.
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lowered sequence has more than 1 user
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Pretend that regmask interference ends at the 'dead' slot, even when
there is other interference ending at the 'reg' slot of the same
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150531 91177308-0d34-0410-b5e6-96231b3b80d8
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Perform all comparisons at instruction granularity, and make sure
register masks on uses count in both gaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150530 91177308-0d34-0410-b5e6-96231b3b80d8
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Only accept register masks when looking for an 'overlapping' def. When
Overlap is not set, the function searches for a proper definition of
Reg.
This means MI->modifiesRegister() considers register masks, but
MI->definesRegister() doesn't.
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When a physreg is live in to a basic block, look for any instruction in
the block that clobbers the physreg.
The instruction doesn't have to properly redefine the register, any
overlapping clobber is OK.
This slightly changes live ranges when compiling with register masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150528 91177308-0d34-0410-b5e6-96231b3b80d8
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The old DenseMap hashed order was very confusing.
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all return type warnings.
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Patch by Matt Johnson
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The MachO back-end needs to emit the garbage collection flags specified in the
module flags. This is a WIP, so the front-end hasn't been modified to emit these
flags just yet. Documentation and front-end switching to occur soon.
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only be live in to a block if it is the function entry point or a landing pad.
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that are greater than the vector element type. For example BUILD_VECTOR
of type <1 x i1> with a constant i8 operand.
This patch fixes the assertion.
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vector_shuffles shouldn't reach isel.
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consistency with setExceptionPointerRegister(...).
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This folds a simple loop tail into a loop latch. It covers the common (in fortran) case of postincrement loops. It's a "free" way to expose this type of loop to downstream loop optimizations that bail out on non-canonical loops (getLoopLatch is a heavily used check).
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marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.
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The scheduler will sometimes check the implicit-def list on instructions
to properly handle pre-colored DAG edges.
Also check any register mask operands for physreg clobbers.
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(but not of) a block pointer do not cause the block pointer to
escape. This fixes rdar://10803830.
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Clang patch (flags) will follow shortly.
The run-time library will also follow, but not immediately.
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generate a shuffle node from two vectors of different types.
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copy/paste fiasco.
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