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2012-06-21Add a number of threshold arguments to the SRA pass.Nadav Rotem
A patch by Tom Stellard with minor changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Add a missing llvm.fma -> VFNMS pattern to the ARM backend.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Emit a single _udivmodsi4 libcall instead of two separate _udivsi3 andEvan Cheng
_umodsi3 libcalls if they have the same arguments. This optimization was apparently broken if one of the node was replaced in place. rdar://11714607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158900 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Update regunits in RegisterCoalescer::reMaterializeTrivialDef.Jakob Stoklund Olesen
Old code would only update physreg live intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove spurious typedefs.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove the RenderMachineFunction HTML output pass.Jakob Stoklund Olesen
I don't think anyone has been using this functionality for a while, and it is getting in the way of refactoring now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove the -live-regunits command line option.Jakob Stoklund Olesen
Register allocators depend on it being permanently enabled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix some more LiveInterval enumerations.Jakob Stoklund Olesen
Deterministically enumerate the virtual registers instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158872 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove LiveIntervalUnions from RegAllocBase.Jakob Stoklund Olesen
They are living in LiveRegMatrix now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158868 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Convert RAGreedy to LiveRegMatrix interference checking.Jakob Stoklund Olesen
Stop depending on the LiveIntervalUnions in RegAllocBase, they are about to be removed. The changes are mostly replacing register alias iterators with regunit iterators, and querying LiveRegMatrix instrad of RegAllocBase. InterferenceCache is converted to work with per-regunit LiveIntervalUnions, and it checks fixed regunit interference separately, using the fixed live intervals provided by LiveIntervalAnalysis. The local splitting helper calcGapWeights() is also considering fixed regunit interference which is kept on the side now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Convert RABasic to using LiveRegMatrix interference checking.Jakob Stoklund Olesen
Stop using the LiveIntervalUnions provided by RegAllocBase, they will be removed soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Enable register unit liveness by default.Jakob Stoklund Olesen
Soon we won't need to compute live intervals for physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158865 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Teach PBQPBuilder::build() about regunit interference.Jakob Stoklund Olesen
Filter out physreg candidates with regunit interferrence. Also compute regmask interference more efficiently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Avoid iterating with LiveIntervals::iterator.Jakob Stoklund Olesen
That is a DenseMap iterator keyed by pointers, so the iteration order is nondeterministic. I would like to replace the DenseMap with an IndexedMap which doesn't allow iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158856 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Revert r158846.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka
that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove an "else" that snuck in after a "return" ;)Kaelyn Uhrain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Check that a file is not a directory before reading it into a MemoryBuffer.Kaelyn Uhrain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add users of a MERGE_VALUE node to the worklist to process again when the ↵Pete Cooper
node is removed. Sorry, no test case. Foudn it by inspection of the code git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Only update regunit live ranges that have been precomputed.Jakob Stoklund Olesen
Regunit live ranges are computed on demand, so when mi-sched calls handleMove, some regunits may not have live ranges yet. That makes updating them easier: Just skip the non-existing ranges. They will be computed correctly from the rescheduled machine code when they are needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20replace usage of EmitGEPOffset() with TargetData::getIndexedOffset() when ↵Nuno Lopes
the GEP offset is known to be constant. With this change, we avoid relying on the IR Builder to constant fold the operations. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Delete dead code.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix DAGCombine to deal with ext-conversion of pre/post_inc loads.Hal Finkel
The test case for this will come with the PPC indexed preinc loads commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158822 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fixing a compiler warning in MSVC 10.Aaron Ballman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove 'static' from inline functions defined in header files.Chandler Carruth
There is a pretty staggering amount of this in LLVM's header files, this is not all of the instances I'm afraid. These include all of the functions that (in my build) are used by a non-static inline (or external) function. Specifically, these issues were caught by the new '-Winternal-linkage-in-inline' warning. I'll try to just clean up the remainder of the clearly redundant "static inline" cases on functions (not methods!) defined within headers if I can do so in a reliable way. There were even several cases of a missing 'inline' altogether, or my personal favorite "static bool inline". Go figure. ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix two rather subtle internal vs. external linker issues.Chandler Carruth
I'll admit I'm not entirely satisfied with this change, but it seemed the cleanest option. Other suggestions quite welcome The issue is that the traits specializations have static methods which return the typedef'ed PHI_iterator type. In both the IR and MI layers this is typedef'ed to a custom iterator class defined in an anonymous namespace giving the types and the functions returning them internal linkage. However, because the traits specialization is defined in the 'llvm' namespace (where it has to be, specialized template lives there), and is in turn used in the templated implementation of the SSAUpdater. This led to the linkage conflict that Clang now warns about. The simplest solution to me was just to define the PHI_iterator as a nested class inside the trait specialization. That way it still doesn't get scoped widely, it can't be accidentally reused somewhere, etc. This is a little gross just because nested class definitions are a little gross, but the alternatives seem more ad-hoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add predicate check around some patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add predicate check around some patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Don't insert 128-bit UNDEF into 256-bit vectors. Just keep the 256-bit ↵Craig Topper
vector. Original patch by Elena Demikhovsky. Tweaked by me to allow possibility of covering more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20A new algorithm for computing LoopInfo. Temporarily disabled.Andrew Trick
-stable-loops enables a new algorithm for generating the Loop forest. It differs from the original algorithm in a few respects: - Not determined by use-list order. - Initially guarantees RPO order of block and subloops. - Linear in the number of CFG edges. - Nonrecursive. I didn't want to change the LoopInfo API yet, so the block lists are still inclusive. This seems strange to me, and it means that building LoopInfo is not strictly linear, but it may not be a problem in practice. At least the block lists start out in RPO order now. In the future we may add an attribute or wrapper analysis that allows other passes to assume RPO order. The primary motivation of this work was not to optimize LoopInfo, but to allow reproducing performance issues by decomposing the compilation stages. I'm often unable to do this with the current LoopInfo, because the loop tree order determines Loop pass order. Serializing the IR tends to invert the order, which reverses the optimization order. This makes it nearly impossible to debug interdependent loop optimizations such as LSR. I also believe this will provide more stable performance results across time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Unbreak the MSVC build: add return to unimplemented functions.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Move the implementation of LoopInfo into LoopInfoImpl.h.Andrew Trick
The implementation only needs inclusion from LoopInfo.cpp and MachineLoopInfo.cpp. Clients of the interface should only include the interface. This makes the interface readable and speeds up rebuilds after modifying the implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add permissions(), map_file_pages(), and unmap_file_pages() to llvm::sys::fs ↵Nick Kledzik
and add unit test. Unix is implemented. Windows side needs to be implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Don't assert when given an empty range.Kaelyn Uhrain
llvm::RawMemoryObject handles empty ranges just fine, and the assert can be triggered in the wild by e.g. invoking clang with a file that included an empty pre-compiled header file when clang has been built with assertions enabled. Without assertions enabled, clang will properly report that the empty file is not a valid PCH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add regunit liveness support to LiveIntervals::handleMove().Jakob Stoklund Olesen
When LiveIntervals is tracking fixed interference in regunits, make sure to update those intervals as well. Currently guarded by -live-regunits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Tidy up.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add an ensureMaxAlignment() function to MachineFrameInfo (analogous toChad Rosier
ensureAlignment() in MachineFunction). Also, drop setMaxAlignment() in favor of this new function. This creates a main entry point to setting MaxAlignment, which will be helpful for future work. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add DAG-combines for aggressive FMA formation.Lang Hames
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-1980 col.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen
The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Style: Don't reuse variables for multiple purposes.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Fix PR13148, an inf-loop in StringMap.Chandler Carruth
StringMap suffered from the same bug as DenseMap: when you explicitly construct it with a small number of buckets, you can arrange for the tombstone-based growth path to be followed when the number of buckets was less than '8'. In that case, even with a full map, it would compare '0' as not less than '0', and refuse to grow the table, leading to inf-loops trying to find an empty bucket on the next insertion. The fix is very simple: use '<=' as the comparison. The same fix was applied to DenseMap as well during its recent refactoring. Thanks to Alex Bolz for the great report and test case. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Emit TableGen's header comment with C-style comments, so it can be used from ↵Benjamin Kramer
C89 code. Should silence warnings when compiling the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158723 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung
The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Mark most PPC register classes to avoid write-after-write.Hal Finkel
For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19[Support/PathV2] Fix out of bounds access in identify_magic when the file is ↵Michael J. Spencer
empty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Make MipsLongBranch::runOnMachineFunction return true.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158702 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Use MachineBasicBlock::instr_iterator instead of MachineBasicBlock::iterator inAkira Hatanaka
MipsCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add support for generating reg+reg preinc stores on PPC.Hal Finkel
PPC will now generate STWUX and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
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