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2012-07-11ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren
It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Patch for Mips direct object generation.Jack Carter
When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11This change removes an "initialization" warning.Jack Carter
Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11In MemoryBuffer::getOpenFile() don't verify that the mmap'edArgyrios Kyrtzidis
file buffer is null-terminated. If the file is smaller than we thought, mmap will not allow dereferencing past the pages that are enough to cover the actual file size, even though we asked for a larger address range. rdar://11612916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka
order of binary encoding. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11[x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier
comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren
When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng
r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to a copy: r1026 = copy r1024 This is correct. However it uses TII->isCoalescableExtInstr() which can return true for instructions which essentially does a sext_in_reg so this can end up with an illegal copy where the source and destination register classes do not match. Add a check to avoid it. Sorry, no test case possible at this time. rdar://11849816 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.Benjamin Kramer
This caused 6 of 65k possible 8 bit udivs to be wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier
to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, ↵Nadav Rotem
allow loads/stores of 64bit values from xmm registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, ↵Nadav Rotem
Ptr, etc. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Remove unused variable.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Refactor the DAG Legalizer by extracting the legalization ofNadav Rotem
Load and Store nodes into their own functions. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns ↵Owen Anderson
an MVT::i1, i.e. before type legalization. This is a speculative fix for a problem on Mips reported by Akira Hatanaka. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Lower RETURNADDR node in Mips backend.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 Mips specific inline asm operand modifier 'L'.Jack Carter
Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Require and preserve LoopInfo for early if-conversion.Jakob Stoklund Olesen
It will surely be needed by heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Teach the LiveInterval::join function to use the fast merge algorithm,Chandler Carruth
generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Run early if-conversion in domtree post-order.Jakob Stoklund Olesen
This ordering allows nested if-conversion without using a work list, and it makes it possible to update the dominator tree on the fly as well. Any erased basic blocks will always be dominated by the current post-order position, so the domtree can be pruned without invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier
X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth
back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem
multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Reverse assembler/disassembler operand order for gather instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add an efficient merge operation to LiveInterval and use it to avoidChandler Carruth
quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Teach LiveIntervals how to verify themselves and start using it in someChandler Carruth
of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10ARM: Allow more flexible patterns in NEON formats.Jim Grosbach
Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Delete code for folding undefs in ScalarEvolution. It's invalid inDan Gohman
obscure ways, and it isn't actually important in the real world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Revert r159938 (and r159945) to appease the buildbots.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09indentationAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson
move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Reapply r158846.Akira Hatanaka
Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09instcombine: merge the functions that remove dead allocas and dead ↵Nuno Lopes
mallocs/callocs/... This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :) In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Some formatting to keep Clang happyRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Oops - correct broken disassembly for VMOVRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Spelling!Richard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton
three-register dp instructions where permissable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07Tweak spelling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07X86: Fix optimizeCompare to correctly check safe condition.Manman Ren
It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07Use the DebugInfo wrappers instead of mucking about with the MDNode directly.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Print the name last.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier
should be camel case, and start with a lower case letter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877 91177308-0d34-0410-b5e6-96231b3b80d8
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