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This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
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mode".
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The coalescer can in very rare cases leave too large live intervals around after
rematerializing cheap-as-a-move instructions.
Linear scan doesn't really care, but live range splitting gets very confused
when a live range is killed by a ghost instruction.
I will fix this properly in the coalescer after 2.9 branches.
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map, reserve space early to avoid rehashing.
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the percentage of time spent in CodeGenPrepare when llcing 403.gcc from 12.6% to
1.8% of total llc time.
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regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
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possible. This goes into instcombine and instsimplify because instsimplify
doesn't need to check hasOneUse since it returns (almost exclusively) constants.
This fixes PR9343 #4 #5 and #8!
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true/false or "icmp slt/sge Y, 0".
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The global cost is the sum of block frequencies for spill code that must be
inserted because preferences weren't met.
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pattern.
This simplifies the code and makes it faster too.
The interference patterns are saved for each candidate register. It will be
reused for actually executing the split. Work in progress.
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free register.
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Patch by Johannes Schaub!
Fixes PR8548
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It gives better results. Sometimes, a live range can be large and still have
high spill weight. Such a range should not be spilled.
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16-bit field. Patch by Akira Hatanaka
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bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.
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Stankovic
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that contain only letters, digits and the characters "_" and ".".
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Patch by Akira Hatanaka
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inefficient file system buffering if the writes are not a multiple of the desired
buffer size. Avoid this by limiting the large write to a multiple of the buffer
size and copying the remainder into the buffer.
Thanks to Dan for pointing this out.
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Initially, slot indexes are quad-spaced. There is room for inserting up to 3
new instructions between the original instructions.
When we run out of indexes between two instructions, renumber locally using
double-spaced indexes. The original quad-spacing means that we catch up quickly,
and we only have to renumber a handful of instructions to get a monotonic
sequence. This is much faster than renumbering the whole function as we did
before.
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individual variable's info from merged global.
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instruction.
You can't really predict how many indexes will be needed from the number of
defs, so let's keep it simple.
Also remove an extra empty index that was inserted after each basic block. It
was intended for live-out ranges, but it was never used that way.
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directly instead of doing many buffer-sized writes.
This caps the number of write(2) calls per string to a maximum of 2.
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by Akira Hatanaka
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Hatanaka, Akira
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correct
type after type legalization has completed. Before then it may simply not be big
enough to hold the shift amount, particularly on x86 which uses a very small type
for shifts (this issue broke stuff in the past which is why LegalizeTypes carefully
uses a large type for shift amounts).
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There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
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A 'load <4 x i32>* null' crashes llc before this fix.
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in the urem case, though not the other way around. This is enough to get #3 from
PR9343!
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"icmp pred %X, CI" and a number of examples where "%X = binop %Y, CI2".
Some of these cases (div and rem) used to make it through opt -O2, but the
others are probably now making code elsewhere redundant (probably instcombine).
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Avoid colliding with the sentinels, hopefully unbreaking
llvm-gcc-x86_64-linux-selfhost.
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Fix the PendingQueue, then disable it because it's not required for
the current schedulers' heuristics.
Fix the logic for the unused list-ilp scheduler.
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