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alloca as both integer and floating-point vectors of the same size. Bugpoint is
not cooperating with me, but I'll try to find a manual testcase tomorrow.
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gave up when I realized I couldn't come up with a good name for what the
refactored function would be, to describe what it does.
This is PR9343 test12, which is test3 with arguments reordered. Whoops!
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a union of a float, <2 x float>, and <4 x float>. This mostly comes up with the
use of vector intrinsics, especially in NEON when programmers know the layout of
the register file. This enables codegen to eliminate a lot of the subregister
traffic it would otherwise generate.
This commit only enables this for a small number of floating-point cases, but a
lot more integer cases. I assume this is okay for all ports, but I did not do
extensive testing of the quality of code involving i512 vectors and the like. If
there is a use case where this generates worse code than before, let me know and
we can scale it back.
This fixes <rdar://problem/9036264>.
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more complicated.
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INT_MIN % -1.
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This will we used for keeping register allocator data structures up to date
while LiveRangeEdit is trimming live intervals.
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reachable uses, but there still might be uses in dead blocks. Use the
standard solution of replacing all the uses with undef. This is
a rare case because it's very sensitive to phase ordering in SimplifyCFG.
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* Add tests for VSRI and VSLI.
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* Update the NEON shift instruction test to expect what 'as' produces.
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LiveRangeEdit::eliminateDeadDefs() will eventually be used by coalescing,
splitting, and spilling for dead code elimination. It can delete chains of dead
instructions as long as there are no dependency loops.
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the sorted array.
Patch by Olaf Krzikalla!
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with this before since none of the register tracking or nightly tests
had unschedulable nodes.
This should probably be refixed with a special default Node that just
returns some "don't touch me" values.
Fixes PR9427
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MSVC 9."
The "fix" was meaningless.
This reverts commit r127245.
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operand for 1.
Found by inspection.
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testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
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This change uses the MaxReorderWindow for both height and depth, which
tends to limit the negative effects of high register pressure.
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expand the testing of the narrowing shift right instructions.
No functionality change.
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Radar 9097659
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In this case, the value need to be available at the load index instead of the
normal use index.
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type.
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This allows LLVM IR using ptx_kernel or ptx_device calling
conventions to be properly printed when emitted in text form.
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then the result could go either way. If it's provably positive then so is the
srem. Fixes PR9343 #7!
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thing for variables.
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the value splatted into every element. Extend this to getTrue and getFalse which
by providing new overloads that take Types that are either i1 or <N x i1>. Use
it in InstCombine to add vector support to some code, fixing PR8469!
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current implementation of -pre-RA-sched=list-ilp.
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corresponds to "add" instruction, not to "sub" as in .pad case
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constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
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because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
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