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virtual. Just inline it into its two current call sites in preparation
for simplifying the code.
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range's weight properly. This is turned off right now in the sense that
you'll get an assert if you get into a situation that can only be caused
by an iterative coalescer. All other code paths operate exactly as
before so there is no functional change with this patch. The asserts
should be disabled if/when an iterative coalescer gets added to trunk.
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pool entry will require relocations against it. I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.
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getAnalysisIfAvailable<TargetData>.
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to help support use when TargetData is not available.
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their appropriate sections before the code itself. They need to be emitted
before the function because on some targets (x86 but not x86_64) the later
may reference a JT or CP entry address
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(x pred y) with more thorough code that does more complete canonicalization
before resorting to range checks. This helps it find more cases where
the canonicalized expressions match.
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depends on XS1A, but I think the ReadOnlySection is already set up for this
and there is no testcase that this breaks. If this is really needed, we can
add the appropriate parameterization to TargetAsmInfo in the future to support
this.
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LLVM IR, it should be rejected by a front-end.
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to twist your brain to see it, I believe it is the same as ELFTargetAsmInfo::SelectSectionForGlobal.
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the generic ELF version instead. This will result in its mergable constant
sections getting named ".rodata.cst4" instead of ".cp.const4", but the
linker looks at the section flags, not the name of the section AFAICT.
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implemented exactly the same way as its ELFTargetAsmInfo subclass
has them.
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be useful, and it's currently unused. (Some issues: it isn't actually
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)
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this:
%ESI<def> = MOV32rr %EDI<kill>
ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
%reg1027<def> = MOVZX64rr32 %ESI
%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
%RDI<def> = MOV64rr %RSP
%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
%RSP<def> = MOV64rr %RDI
into this:
4 %reg1024<def> = MOV32rr %EDI<kill>
12 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20 %reg1025<def> = MOVZX64rr32 %reg1024
28 %reg1026<def> = MOV64rr %reg1025<kill>
36 %reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44 %reg1027<def> = MOV64rr %reg1026<kill>
52 %reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60 %reg1028<def> = MOV64rr %RSP
68 %reg1029<def> = MOV64rr %reg1028<kill>
76 %reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84 %RSP<def> = MOV64rr %reg1029
This helps greatly when debugging register allocation and coalescing
problems.
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and call PrintGlobalVariable, allowing elimination and simplification
of various targets.
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MachineBasicBlock. We'll use these shortly.
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chain to the super class instead of initializing mangler directly.
This gives it .file and module level inline asm support among other
things.
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This eliminates redundancy setting up the mangler and adds support to them
for module-level inline asm and a .file directive.
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LLVM IR concept.
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vectors needlessly, doxygenify comments, improve constness, etc.
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as much, etc.
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ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.
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global declared symbols are initialized with references from other global
symbols.
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Callanan.
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Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
(srl (and x, (shl -1, c1)), (sub c1, c2))
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