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2012-03-07misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick
ScheduleDAGInstrs will be the main interface for MI-level schedulers. Make sure it's readable: one page of protected fields, one page of public methids. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched prep: remove extra "protected"Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched prep: rename InsertPos to End.Andrew Trick
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
We had half the API with one convention, half with another. Now was a good time to clean it up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Copy the right amount of elements.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07SmallPtrSet: Copy all the elements when swapping, not just numelements.Benjamin Kramer
This fixes a build failure in webkit. Copying all elements shouldn't be necessary, I'll look out for a better fix soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier
condition flags to CPSR. This allows us to simplify SelectCmp. Patch by Zonr Chang <zonr.xchg@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Fix infinite loop in nested multiclasses.Jakob Stoklund Olesen
Patch by Michael Liao! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Try to clarify this comment some.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Remove another outbreak of customized (and completely broken) hashing.Chandler Carruth
This one is particularly annoying because the hashing algorithm is highly specialized, with a strange "equivalence" definition that subsets the fields involved. Still, this looks at the exact same set of data as the old code, but without bitwise or-ing over parts of it and other mixing badness. No functionality changed here. I've left a substantial fixme about the fact that there is a cleaner and more principled way to do this, but it requires making the equality definition actual stable for particular types... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Where the BranchFolding pass removes a branch then adds another better branch,Bill Wendling
the DebugLoc information can be maintained throughout by grabbing the DebugLoc before the RemoveBranch and then passing the result to the InsertBranch. Patch by Andrew Stanford-Jason! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Fix cmakeAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152210 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ScheduleDAGInstrs commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule emission.Andrew Trick
ScheduleDAG has nothing to do with how the instructions are scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule printing.Andrew Trick
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule verification.Andrew Trick
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Switch this code to use hash_combine_range rather than incremental callsChandler Carruth
to hash_combine. One of the interfaces could already do this, and the other can just use a small buffer. This is a much more efficient way to use the hash_combine interface, although I don't have any particular benchmark where this code was hot, so I can't measure much of an impact. It at least doesn't slow anything down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cache the sized-ness of struct types, once we reach the steady state ofChandler Carruth
"is sized". This prevents every query to isSized() from recursing over every sub-type of a struct type. This could get *very* slow for extremely deep nesting of structs, as in 177.mesa. This change is a 45% speedup for 'opt -O2' of 177.mesa.linked.bc, and likely a significant speedup for other cases as well. It even impacts -O0 cases because so many part of the code try to check whether a type is sized. Thanks for the review from Nick Lewycky and Benjamin Kramer on IRC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152197 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07No functionality change. Type::isSized() can be expensive, so avoid calling itNick Lewycky
until after other inexpensive tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Added -view-background to avoid waiting for each GraphViz invocation.Andrew Trick
GV and XDOT paths are untested but should work the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Added -view-misched=dags options.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick
Soon, ScheduleDAG will not refer to the BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Added MachineBasicBlock::getFullName() to standardize/factor codegen ↵Andrew Trick
diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick
the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched: Use the StartBlock/FinishBlock hooksAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Add the DW_AT_APPLE_runtime_class attribute to forward declarationsEric Christopher
as well as completely defined classes. This fixes rdar://10956070 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng
performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach
Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Hoist common code out of if statement.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06SmallPtrSet: Provide a more efficient implementation of swap than the ↵Benjamin Kramer
default triple-copy std::swap. This currently assumes that both sets have the same SmallSize to keep the implementation simple, a limitation that can be lifted if someone cares. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Tidy up. Kill some dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Allow the same types in DPair as in QPR.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Convert PowerPC to register mask operands.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Change ConstantAggrUniqueMap to use Chandler's new hashingJay Foad
implementation. Patch by Meador Inge git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen
When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Avoid finalizeBundles infinite looping.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson
providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames
The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05A few more cases of missing masking in ComputeMaskedBits; found by inspection.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152070 91177308-0d34-0410-b5e6-96231b3b80d8
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